MBIST Controller ECC Parity Logic In-Field Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional systems lack a mechanism to execute Check the Checker (CTC) on ECC/Parity logic using MBIST vectors, resulting in reduced diagnostic coverage and longer test execution times, which can lead to system failures in safety-critical applications.
Innovation Solution
The proposed solution utilizes an MBIST controller to generate and log test vectors for both memory and ECC/Parity logic, allowing for parallel testing to shorten diagnostic time and enhance coverage, particularly in safety-critical IP components, and includes a hardware-based solution that can operate independently without platform-level components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional separate testing of memory and ECC/Parity logic is performed, then test execution time is extended, but diagnostic coverage is reduced
Solution Approach 1:
The patent merges the testing of memory arrays and ECC/Parity logic into a single integrated MBIST process. The MBIST controller simultaneously generates test vectors for both memory and diagnostic components, combining what were previously separate testing operations into one unified test execution flow, thereby achieving both time reduction and enhanced diagnostic coverage
Solution Approach 2:
The patent implements continuous parallel testing where the MBIST controller continuously generates and processes test vectors for both memory and ECC/Parity logic without interruption or sequential waiting. This continuous action eliminates idle time between test phases and maintains full diagnostic capability throughout the entire test duration
2Reliability
If Check the Checker (CTC) testing on ECC/Parity logic is not executed, then test execution time is shortened, but system reliability in safety-critical applications deteriorates
Solution Approach 1:
The MBIST controller performs self-service by automatically generating test vectors for ECC/Parity logic without requiring external testing equipment or additional test controllers. The system tests its own diagnostic components using internally generated test patterns, eliminating the need for separate external testing operations and associated time delays
Solution Approach 2:
The MBIST controller is designed with multi-functionality to handle both memory array testing and ECC/Parity logic testing through a single unified interface. This universal testing capability allows the same controller to perform diverse diagnostic functions without requiring specialized testing equipment for each component type
3Ease of manufacture
If platform-level components are required for testing, then device complexity increases, but ease of manufacture decreases
Solution Approach 1:
The patent extracts the testing functionality from external platform-level components and relocates it directly into the MBIST controller integrated circuit. By taking out the test vector generation and control logic from external sources and embedding it within the device itself, the system eliminates dependencies on external testing infrastructure and simplifies the manufacturing process
Solution Approach 2:
The MBIST controller acts as an intermediary that directly interfaces with both memory arrays and ECC/Parity logic without requiring external platform components. This intermediary role is fulfilled by the integrated controller that mediates between test vector generation and the diagnostic components being tested, eliminating the need for external testing equipment
Data Source
AI summary
The disclosed embodiments relate to method, apparatus and system for testing memory circuitry and diagnostic components designed to test the memory circuitry. The memory may be tested regularly using Memory Built-In Self-Test (MBIST) to detect memory failure. Error Correction Code (ECC)/Parity is implemented for SRAM/Register Files/ROM memory structures to protect against transient and permanent faults during runtime. ECC/Parity encoder and decoder logic detect failure on both data and address buses and are intended to catch soft error or structural fault in address decoding logic in SRAM Controller, where data may be read/written from/to different locations due to faults. ECC/parity logic on the memory structures are subject to failures. In certain exemplary embodiments, an array test controller is used to generate and transmit error vectors to thereby determine faulty diagnostic components. The test vectors may be generated randomly to test the diagnostic components during run-time for in-field testing.