MBIST Circuit DDR and PBT Testing for DRAM Repair
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Solution Overview
Problem
Semiconductor memory devices, particularly DRAMs, face challenges in reliability and increased error rates due to downsizing, leading to performance disruptions and availability constraints in data centers, necessitating effective testing and repair methods to maintain system stability and efficiency.
Innovation Solution
A method and circuit for a memory built-in self-test (MBIST) that performs double data rate (DDR) and parallel bit (PBT) tests, using an internal clock signal to detect and repair defective cells with redundancy cells, and verifies the repair operation through re-testing, while also testing architectural requirements of the memory physical layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If comprehensive testing is performed on all memory banks to ensure reliability, then defect detection capability is improved, but test time increases significantly
Solution Approach 1:
The patent applies partial action by performing DDR tests on only one selected memory bank instead of all banks, while still achieving effective defect detection through the combination of DDR and PBT test modes. This selective testing approach reduces test time while maintaining reliability through the complementary nature of the two test methods.
Solution Approach 2:
The patent segments the testing process into two distinct test modes (DDR test and PBT test) that can be selectively applied. By dividing the memory system into individual banks and selecting only one bank for DDR testing, the overall test time is reduced while maintaining comprehensive defect detection coverage through the PBT mode.
2Quantity of substance
If memory device capacity is increased to meet data center requirements, then storage capability is improved, but test complexity and time increase
Solution Approach 1:
For high-capacity memory devices with multiple banks, the patent applies partial action by configuring the MBIST circuit to test only one bank using DDR mode while other banks are tested using PBT mode. This selective approach reduces test complexity and time for large-capacity devices without compromising overall defect detection effectiveness.
Solution Approach 2:
The patent changes the test parameters by introducing an MBIST option that allows selection between DDR test mode and PBT test mode. This parameter change enables adaptive testing strategies for different memory capacities, reducing test complexity for high-capacity devices while maintaining detection capability.
3Reliability
If repair operations are performed for defective cells, then reliability is improved, but test and verification time increases
Solution Approach 1:
The patent extracts and isolates defective cells through the PBT test mode, which can identify defective cells in all banks simultaneously. By separating the defect detection function (PBT) from the verification function (re-test), the system efficiently manages repair operations without significantly increasing overall test time.
Solution Approach 2:
The patent implements feedback through re-testing after repair operations. The MBIST circuit performs re-tests on repaired cells to verify repair effectiveness, creating a closed-loop system that ensures reliability while minimizing verification time through targeted re-testing of only the repaired cells.
Data Source
AI summary
A method of testing a memory device, a memory built-in self-test (MBIST) circuit, and a memory device for improving reliability and reducing a test time. The memory device includes a plurality of memory banks and the MBIST circuit. The MBIST circuit is configured to generate double data rate (DDR) test patterns and parallel bit test (PBT) test patterns to test the memory banks. When a defective cell is detected as a result of the PBT test or the DDR test, the MBIST circuit is configured to perform a repair operation for replacing the defective cell with a redundancy cell and perform a re-test to verify the repair operation. The MBIST circuit may be configured to perform the DDR test on one or more memory cells including the defective cell during the re-test.