MBIST Masking Element for ECC Logic Fault Injection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current testing methods for System on a Chip (SoC) memory error correction code logic are inadequate, particularly during manufacturing test (MFGT), power-on-self-test (POST), and mission mode self-test (MMST phases, as they fail to thoroughly test ECC logic and its interfaces, leading to potential undetected errors that can be critical in safety applications.
Innovation Solution
An improved Memory Built-in Self-Test (MBIST) diagnostics system that includes a masking element to inject faults into logical memory modules and a data compare unit to determine errors, allowing for comprehensive testing of ECC logic during MFGT and POST phases, ensuring the ECC logic is functioning correctly before normal operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing methods (MBIST and ATPG) are used separately for memory and logic, then manufacturing test coverage is achieved, but ECC logic and functional paths between memory and logic remain untested
Solution Approach 1:
The patent combines MBIST and ATPG into a unified testing system that can simultaneously test memory arrays, ECC logic, and functional paths. The system integrates memory built-in self-test capabilities with automatic test pattern generation, allowing comprehensive coverage of previously untestable regions through a single coordinated testing architecture.
Solution Approach 2:
The testing system is designed to perform multiple functions: testing physical memory modules, testing logical memory modules with ECC, and testing functional paths between memory and logic. This multi-functional approach eliminates the need for separate testing strategies and achieves comprehensive coverage across all testing phases.
2Reliability
If scan segments are embedded in memories to test functional paths, then path testing capability is improved, but memory area increases
Solution Approach 1:
The patent extracts the scanning capability from the memory array structure itself and implements it as a separate, coordinated function between MBIST and ATPG components. This allows functional paths to be tested without embedding scan chains within the memory, thereby avoiding the area penalty while maintaining path testing capability.
3Reliability
If MBIST connects and controls functional paths directly, then functional path testing is improved, but function timing is impacted by additional multiplexing
Solution Approach 1:
The patent introduces an intermediary coordination layer that enables MBIST and ATPG to work together without direct MBIST control of functional paths. This intermediary mechanism allows functional paths to be tested through coordinated pattern generation and response capture, avoiding the timing degradation caused by direct MBIST multiplexing while maintaining comprehensive path coverage.
4Reliability
If ATPG RAM sequential is used to push patterns through memories, then functional path testing is achieved, but it can only be used in MFGT phase not POST and MMST
Solution Approach 1:
The unified testing system is designed to operate across all three testing phases (MFGT, POST, and MMST) by integrating the capabilities of both MBIST and ATPG. The system adapts its operation mode depending on the phase, providing comprehensive functional path coverage in manufacturing while also enabling post-assembly and mission-mode testing that were previously unavailable.
Data Source
AI summary
Systems and methods disclosed herein provide for improved testing of memory error correction code (“ECC”) logic with memory built-in self-test (“MBIST”). Embodiments provide for a masking element to inject one or more faults into the ECC logic during at least one of a manufacturing test (“MFGT”) and a power-on-self-test (“POST”), wherein, based on the injected faults, it can be determined if the ECC logic contains any errors.