MBIST Logic Testing ECC and Physical Memory
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Solution Overview
Problem
Current memory component testing in integrated circuits is inefficient, as the Error Correction Code (ECC) logic is not tested on-board after manufacturing, and the reliability of both ECC logic and physical memory is not thoroughly verified, especially in high-risk industries where zero-defect policies are mandatory, leading to potential failures and safety concerns.
Innovation Solution
A method and apparatus that allow on-board testing of both physical memory and ECC logic using the same MBIST logic, enabling switching between different testing views without additional complex logic, thereby ensuring comprehensive and reliable testing of memory components post-manufacture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC logic is not tested on-board after manufacturing, then device complexity is reduced, but reliability deteriorates
Solution Approach 1:
The MBIST logic is designed to perform multiple testing functions: it can test both the physical memory and the ECC logic by switching between different test modes. This multi-functionality eliminates the need for separate dedicated test logic for ECC, thereby improving reliability without proportionally increasing device complexity
Solution Approach 2:
The test system incorporates dynamic routing logic that can reconfigure signal paths based on test mode requirements. By making the routing dynamic rather than static, the same physical infrastructure can adapt to test different components (memory or ECC) without requiring separate dedicated paths, thus avoiding complexity increase
2Reliability
If separate test logic is added for ECC testing, then reliability is improved, but device complexity increases
Solution Approach 1:
Instead of adding separate dedicated test logic for ECC, the patent makes the existing MBIST logic universal by enabling it to test both memory and ECC through mode switching. This approach achieves comprehensive testing coverage without the complexity penalty of duplicate test infrastructure
Solution Approach 2:
The patent merges the testing capabilities for memory and ECC into a single unified test system. By combining both testing functions into one MBIST framework with shared resources (registers, routing logic, control mechanisms), it eliminates redundancy and avoids the complexity that would result from separate independent test systems
3Reliability
If comprehensive testing of both memory and ECC is implemented, then reliability is improved, but ease of manufacture deteriorates
Solution Approach 1:
The MBIST logic serves as a universal testing platform that handles both memory and ECC testing through software/firmware mode switching rather than requiring separate hardware test infrastructures. This universality simplifies the manufacturing process by using a single test methodology and infrastructure for both components
Solution Approach 2:
The patent uses virtual/test logic representations (copies) of the physical memory and ECC structures within the MBIST framework. These virtual models allow comprehensive testing without requiring additional physical test hardware, thereby maintaining ease of manufacture while achieving thorough verification
Data Source
AI summary
Method and apparatus for testing the memory components of an integrated Circuit (IC) using a routing logic and a built-in design for test (DFT) hardware processing device. Based on input provided from an interface controller to the IC, the IC is tested according to one of at least two modes. In a first mode, the built-in DFT hardware processing device executes a test that checks for faults in the physical memory of the IC. In a second mode, the built-in DFT hardware processing device executes a test that checks for faults in the error correction logic of the IC. By using the same routing logic and built-in DFT hardware processing device, tests of the memory components according to the first and second mode can be executed on an automatic and serial basis, even after the manufacture of the IC.