MBIST ECC Integration for Memory Yield Improvement
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Solution Overview
Problem
Conventional memory built-in self-testing (MBIST) techniques do not effectively detect or repair errors, particularly due to the lack of error correcting code (ECC) usage, which limits the yield of random access memory (RAM).
Innovation Solution
The implementation of memory testing schemes that integrate MBIST with ECC logic to detect and repair errors, using finite state machines (FSMs) for column and row redundancy repair, and ECC for multi-bit error correction, enabling efficient ECC usage to improve memory cell yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional MBIST is used without ECC, then the testing process is simpler, but error detection and repair capability is insufficient
Solution Approach 1:
The patent merges MBIST and ECC into a unified testing framework where MBIST detects errors and ECC repairs them. The ECC encoder is integrated into the MBIST path, allowing the same test infrastructure to both detect and correct errors, thereby improving reliability without proportionally increasing complexity.
Solution Approach 2:
The testing infrastructure is designed to serve multiple functions: MBIST performs error detection while the integrated ECC logic performs error repair. This multi-functionality allows a single system to handle both detection and correction, improving error repair capability while avoiding the need for entirely separate testing and correction systems.
2Reliability
If ECC is integrated with MBIST, then error repair capability improves, but device complexity increases
Solution Approach 1:
The patent combines MBIST detection logic with ECC correction logic into a single integrated testing system. The ECC encoder is placed in the data path of MBIST, allowing errors detected during testing to be automatically corrected without requiring separate testing and correction infrastructure, thus limiting the increase in device complexity.
Solution Approach 2:
The integrated MBIST-ECC system performs self-service by automatically detecting and correcting errors during the testing process without external intervention. The system uses its own resources (ECC encoder integrated in the test path) to repair errors, reducing the need for additional complex external testing equipment or manual correction procedures.
3Productivity
If redundancy repair is used for column and row errors, then manufacturing yield improves, but the system requires more complex error accumulation and analysis logic
Solution Approach 1:
The patent implements preliminary error accumulation during the MBIST testing phase, where errors in columns and rows are counted and recorded before the repair decision is made. This preliminary analysis allows the system to identify which columns or rows have excessive errors and should be repaired via redundancy, enabling proactive yield improvement without complex real-time analysis during operation.
Solution Approach 2:
The error analysis is segmented into separate column-wise and row-wise counting operations. The system independently accumulates and analyzes errors in columns and rows separately, then applies appropriate redundancy repair based on which segment has more errors. This segmentation simplifies the overall analysis logic compared to analyzing the entire memory array simultaneously.
Data Source
AI summary
Various implementations described herein refer to a device having an encoder coupled to memory. The ECC encoder receives input data from memory built-in self-test circuitry, generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to memory. The device may have an ECC decoder coupled to memory. The ECC decoder reads the encoded data from memory, generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data, and provides the corrected data and double-bit error flag as output. The ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits, wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data.