MBIST Parity and ECC Logic Integration for Memory Error Checking
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Solution Overview
Problem
Conventional devices lack integrated data protection circuitry in memory built-in self-test (MBIST) hardware, leading to inefficiencies in testing data protection mechanisms and potential propagation of errors due to untested logic faults in parity and ECC circuitry.
Innovation Solution
Integrating parity and ECC generators as part of the MBIST hardware circuitry to test and correct errors in data storage structures, enabling comprehensive data protection testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data protection circuitry is not integrated into MBIST hardware, then device complexity is reduced, but reliability deteriorates due to untested logic faults in parity and ECC circuitry
Solution Approach 1:
The patent integrates data protection circuitry (parity generators, ECC logic) directly into the MBIST hardware structure. This merging allows the MBIST system to simultaneously test memory cells and validate the correctness of data protection operations, ensuring that parity and ECC circuitry function properly without requiring separate testing mechanisms.
Solution Approach 2:
The MBIST hardware is designed to perform multiple functions: it tests memory cell functionality, validates write operations, verifies read operations, and checks data protection circuitry correctness. By making the MBIST system universal, the patent eliminates the need for separate dedicated testing hardware for each function, thereby improving reliability without proportionally increasing device complexity.
2Ease of operation
If separate testing mechanisms are used for data protection circuitry, then device complexity increases, but ease of operation improves due to comprehensive testing capability
Solution Approach 1:
The MBIST system is designed as a universal testing mechanism that handles memory cell testing, write verification, read verification, and data protection circuitry validation all through a single integrated hardware structure. This multi-functionality simplifies operation by providing comprehensive self-testing capability without requiring multiple separate testing systems, thereby improving ease of operation without excessive complexity increase.
Solution Approach 2:
The integrated MBIST system enables the memory device to perform comprehensive self-testing autonomously. The system generates test patterns, applies them to memory cells, validates write operations through parity and ECC checking, and verifies read operations without external intervention. This self-service capability improves ease of operation by allowing the device to validate its own functionality while maintaining a unified hardware structure.
3Productivity
If MBIST runs periodically instead of continuously, then productivity improves, but reliability may deteriorate due to delayed error detection
Solution Approach 1:
The patent implements MBIST as a periodic operation that executes at defined intervals (e.g., during initialization, after reset, or at scheduled maintenance intervals) rather than continuously. This periodic execution maintains productivity by allowing normal operations to proceed between test cycles while still providing reliable error detection at critical intervals. The system balances test execution efficiency with timely error detection by strategically scheduling MBIST runs.
Data Source
AI summary
A processing device used for MBIST is provided which comprises a data storage structure configured to store data, data protection circuitry configured to add at least one protection bit to corresponding portions of the data written to the data storage structure, data protection checking circuitry configured to identify one or more errors made by the data protection circuitry and an MBIST controller configured to receive the corresponding portions of data written to the data storage structure and receive at least one indication identifying the one or more errors.