MBIST Logic Extraction for IC Memory Testability
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Solution Overview
Problem
Traditional methods for adding memory built-in self-test (MBIST) logic to integrated circuit (IC) designs modify the larger module, which can compromise the integrity of intellectual property (IP) and fail to test the integration of memory within the module, leading to performance guarantees issues.
Innovation Solution
The approach involves adding MBIST logic to the IC design at the register transfer level (RTL) or netlist level, coupling it to the physical memory module via a logical boundary of an intermediate level module, thereby preserving the integrity of the intermediate level module and allowing for testing of both the physical memory and intervening logic without modifying the module itself.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MBIST logic is added within the larger module after intervening circuitry, then memory testability is improved, but the integrity of the intermediate level module is compromised and performance guarantees are lost
Solution Approach 1:
The MBIST logic is extracted from the intermediate level module and placed in the top-level module, allowing memory testability to be improved without modifying or compromising the integrity of the intermediate level module. The MBIST logic is applied to the outputs of the intermediate level module rather than being inserted within it.
Solution Approach 2:
The top-level module acts as an intermediary that applies MBIST logic to the outputs of the intermediate level module. This mediator approach allows testing of memory functionality without directly modifying the intermediate level module, thus preserving its integrity and performance guarantees.
2Reliability
If MBIST logic is added within the larger module, then memory testing capability is improved, but the ability to test intervening logic is lost
Solution Approach 1:
The MBIST logic applied at the top-level module provides multi-functional testing capability. It can test both the memory module itself and the intervening logic within the intermediate level module, as the MBIST logic receives and processes outputs from the entire intermediate level module, enabling comprehensive testing of both components.
3Adaptability or versatility
If multiple MBIST logic are used for different memory variations, then coverage of memory types is improved, but device complexity increases
Solution Approach 1:
A single instance of MBIST logic at the top-level module is designed to be universal and adaptable to multiple memory variations. The MBIST logic can accommodate different memory types (e.g., synchronous, asynchronous, dual-port) by configuring its parameters and control signals, eliminating the need for separate MBIST logic instances for each memory variation.
Data Source
AI summary
In one aspect, electronic design automation systems, methods, and non-transitory computer readable media are presented for adding a memory built-in self-test (MBIST) logic at register transfer level (RTL) or at netlist level into an integrated circuit (IC) design. In some embodiments, the MBIST logic is coupled to a physical memory module via a logical boundary of an intermediate level module that contains the physical memory module. The MBIST logic helps to keep intact integrity of the intermediate level module, making it more likely to meet any specified performance of the intermediate level module and reduce area overhead.