Multi-processor MBIST with JTAG Multiplexing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multi-processor core devices require an efficient self-test functionality for their integrated volatile memory, which existing technologies have not adequately addressed, especially in ensuring comprehensive and fast testing during production and runtime.
Innovation Solution
The implementation of a memory built-in self-test (MBIST) system with a finite state machine (FSM), JTAG interface, and configurable BIST controllers for each processor core, allowing independent memory testing and programmable clocking for SRAM and PRAM, enabling comprehensive and flexible self-testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multi-processor core device uses a housing with a high number of pins to allow access to various peripherals, then the device provides increased performance and improved security, but the device complexity increases
Solution Approach 1:
The patent combines multiple processor cores (master core and slave cores) into a single multi-processor system integrated on one chip. This merging approach allows the device to achieve improved security through multiple cores while reducing the need for additional external components and pins, thereby managing device complexity effectively.
Solution Approach 2:
The master core is designed to perform multiple functions: it can execute application code, manage slave cores, control MBIST operations for all cores, and interface with external peripherals. This multi-functionality reduces the need for separate dedicated components, thereby reducing pin count while maintaining security and performance.
2Productivity
If each processor core has its own dedicated memory, then the device provides increased performance, but the manufacturing complexity increases
Solution Approach 1:
The patent divides the memory system into separate dedicated memory blocks for each processor core (master core has master data memory and master program memory; each slave core has slave data memory and slave program memory). This segmentation allows each core to have independent fast access to its own memory, improving performance while using standard memory integration techniques that are manageable in manufacturing.
Solution Approach 2:
The memory architecture uses a hierarchical structure where each core's dedicated memory is nested within the overall system memory hierarchy. The slave cores' memories are loaded through the master core, creating a nested dependency structure that simplifies manufacturing by allowing standardized memory blocks to be integrated systematically.
3Measurement precision
If an MBIST system is implemented for each processor core's memory, then the measurement precision of memory testing is improved, but the device complexity increases
Solution Approach 1:
The patent implements MBIST (Memory Built-In Self-Test) controllers directly associated with each core's memory, allowing the memory systems to test themselves automatically. Each memory block has its own MBIST controller that can independently perform self-diagnosis, providing high measurement precision for memory testing while reducing the need for external test equipment and complex external testing circuits.
Solution Approach 2:
The MBIST controllers for all cores are integrated into the multi-processor system chip, merging the self-test functionality with the main device. This integration allows comprehensive memory testing across all cores while managing complexity through unified control architecture and shared test access ports.
4Ease of operation
If a JTAG interface is coupled with the MBIST access ports of each processor core, then the ease of operation for testing is improved, but the device complexity increases
Solution Approach 1:
The JTAG interface is designed as a universal test access port that can interface with the MBIST access ports of multiple processor cores through multiplexers. This single JTAG interface provides ease of operation for testing all cores' memories, eliminating the need for separate test interfaces for each core, while managing complexity through shared access architecture.
Solution Approach 2:
Multiplexers are used as intermediary components between the JTAG interface and the MBIST access ports of different cores. These multiplexers allow the single JTAG interface to sequentially access multiple MBIST controllers, providing ease of operation for comprehensive testing while reducing the number of direct connections needed, thereby managing device complexity.
Data Source
AI summary
In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.