MBIST Circuitry Parallel Initialization and Burn-in Stress
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Solution Overview
Problem
Integrated circuits with memory built-in self test (MBIST) circuitry face inefficiencies in testing multiple arrays serially, which prolongs initialization time and power-off state transitions, and existing burn-in processes do not effectively pre-stress components for reliability.
Innovation Solution
The integration of MBIST circuitry that enables parallel initialization of multiple arrays and the application of stress and inverse stress vectors during burn-in to expedite initialization and pre-stress memory elements, reducing power consumption and enhancing reliability by maintaining opposing states during burn-in.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serial testing of multiple arrays is performed, then testing completeness is improved, but initialization time increases
Solution Approach 1:
The MBIST circuitry is divided into a master controller and multiple slave circuits, each responsible for specific arrays. This segmentation allows parallel initialization operations across different array groups while maintaining serial testing control, thereby reducing overall initialization time without compromising testing completeness.
Solution Approach 2:
The system performs preliminary parallel initialization of arrays before the actual serial testing process begins. By pre-initializing multiple arrays simultaneously using the master controller's coordination of slave circuits, the system reduces the time required to set up memory elements for testing while ensuring all arrays are properly prepared for subsequent serial testing.
2Speed
If parallel initialization is implemented, then initialization speed is improved, but device complexity increases
Solution Approach 1:
The master MBIST controller is designed with multi-functionality, capable of both serial testing coordination and parallel initialization control. By integrating these functions into a single master unit that communicates with slave circuits, the system achieves parallel initialization capability without proportionally increasing overall circuit complexity.
Solution Approach 2:
Slave circuits act as intermediaries between the master controller and individual arrays. These intermediary components simplify the master controller's burden by handling local initialization operations, enabling parallel initialization across multiple arrays while distributing circuit complexity across modular slave units rather than concentrating it in the master controller.
3Reliability
If stress vectors are applied during burn-in, then reliability is improved, but time required for burn-in increases
Solution Approach 1:
The MBIST circuitry applies stress and inverse stress vectors in periodic alternation during burn-in operations. By cycling between stress conditions and inverse stress conditions, the system accelerates the detection of potential failures and achieves reliable burn-in results more quickly than continuous single-state stress would permit.
Solution Approach 2:
The system dynamically changes the stress state parameters during burn-in by switching between stress vectors and inverse stress vectors. This parameter variation accelerates the burn-in process by forcing memory elements through different operational states that reveal defects more rapidly, reducing the total burn-in time required to achieve desired reliability levels.
Data Source
AI summary
Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.