MBIST Circuitry Parallel Initialization for Pre-Stressed ICs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits with memory built-in self test (MBIST) circuitry face inefficiencies in testing multiple arrays serially, which prolongs initialization time and may not effectively pre-stress components during burn-in operations, potentially leading to undetected failures.
Innovation Solution
The MBIST circuitry is configured to apply stress and inverse stress vectors in parallel to multiple arrays, allowing for rapid initialization and pre-stressing, with a MBIST master circuit controlling slave circuits to input vectors simultaneously, reducing the time required to set memory elements to desired states and enhancing reliability by maintaining opposing states during burn-in.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If arrays are tested serially during MBIST operations, then testing thoroughness is improved, but initialization time increases
Solution Approach 1:
The patent divides the MBIST operation into two distinct modes: serial testing mode for thorough array validation and parallel initialization mode for rapid state setting. The segmentation allows each mode to optimize for its specific function without compromise
Solution Approach 2:
The system dynamically switches between serial and parallel operational modes based on the current task requirement. The MBIST circuitry can adapt its operation from serial (for testing) to parallel (for initialization), providing flexibility to resolve the time-thoroughness contradiction
2Reliability
If stress vectors are applied during burn-in operations, then component reliability is improved, but test duration increases
Solution Approach 1:
The patent applies stress vectors during the burn-in operation before the IC enters normal operation. This preliminary action pre-stresses the components to expose potential failures early, ensuring that only reliable components proceed to normal operation, thus improving overall reliability without extending normal operational duration
Solution Approach 2:
The stress vectors are applied in periodic cycles during burn-in, alternating between stress application and evaluation phases. This periodic approach allows thorough reliability testing while managing the overall test duration through structured intervals
3Productivity
If multiple arrays are initialized in parallel, then initialization speed is improved, but circuit complexity increases
Solution Approach 1:
The MBIST circuitry is designed with multi-functionality, serving both as a controller for parallel initialization and as a tester for serial array validation. This universal design achieves parallel initialization capability without proportionally increasing overall circuit complexity, as the same core circuitry performs multiple functions
Data Source
AI summary
Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, MBST circuitry is used set memory elements of arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage. Preferably, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays.