MBIST Latency Detection via Ping Signal for Memory Self-Test
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Solution Overview
Problem
Current semiconductor device testing methods face challenges in efficiently identifying memory failures due to latency issues and pipeline stage complexities, which complicate the design and verification of memory built-in self-test (MBIST) circuits, leading to increased costs and reduced fault coverage.
Innovation Solution
The implementation of a mechanism to determine and compensate for round trip latency by using a 'ping' signal that experiences the same latency as control and data signals, allowing for accurate association of failure signals with memory read operations, independent of pipeline stage configurations, thereby enhancing design flexibility and fault coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional memory testing methods are used without latency compensation, then the test implementation is simpler, but the fault coverage is reduced and failure signal association is inaccurate
Solution Approach 1:
The patent applies preliminary action by measuring the round trip latency before executing the memory self-test algorithm. The MBIST circuit first determines the latency value through a latency measurement mode, then uses this pre-determined value to accurately associate failure signals with their corresponding memory read operations during the actual test, eliminating the need for complex real-time latency compensation
Solution Approach 2:
The patent segments the MBIST operation into two distinct modes: a latency measurement mode where the round trip latency is determined through ping signals, and a self-test mode where the memory is actually tested using the pre-determined latency value. This segmentation simplifies the overall circuit design by separating the latency determination function from the memory testing function
2Adaptability or versatility
If additional pipeline stages are added to the design, then design flexibility is improved, but the correspondence between failure signals and memory operations becomes inaccurate
Solution Approach 1:
The patent uses parameter changes by dynamically adjusting the operation counter based on the measured round trip latency parameter. When additional pipeline stages are added, the latency measurement automatically captures the new latency value, and the operation counter is相应ly adjusted, allowing the system to maintain accurate failure signal association regardless of pipeline configuration changes
Solution Approach 2:
The patent implements feedback by using the measured round trip latency to control the operation counter during memory read operations. The latency value feeds back into the timing control logic, ensuring that failure signals are associated with the correct memory operations even when pipeline stages are added or modified
3Measurement precision
If complex pipeline balancing techniques are used, then failure signal association is more accurate, but the design and verification effort and costs increase
Solution Approach 1:
The patent applies self-service by enabling the MBIST circuit to automatically measure its own round trip latency and use this information for accurate failure signal association. The circuit performs self-characterization through the latency measurement mode, eliminating the need for external manual timing analysis and complex pipeline balancing techniques
Solution Approach 2:
The patent performs preliminary latency measurement to establish the timing relationship before actual memory testing. This pre-characterization approach replaces complex runtime pipeline balancing with a simple lookup based on pre-determined latency values, significantly reducing design and verification effort
Data Source
AI summary
In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.