MBIST and Scan-Based State Clearing for Secure SoC Logic
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Solution Overview
Problem
The challenge of efficiently clearing the contents of flip-flops and memory in systems-on-chip (SoCs) due to their large number and the impracticality of custom reset logic, which is necessary for enhanced security in cloud systems where multiple users access the same hardware.
Innovation Solution
Utilizing built-in test and scan circuitry, including MBIST and EDT controllers, to perform state clearing of internal memories and flip-flops through an IJTAG and scan network, managed by a security processor to ensure secure and efficient clearing without additional custom logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If custom reset logic is implemented to clear flip-flops and memory, then security is improved, but device complexity and chip space increase
Solution Approach 1:
The patent applies universality by making existing test circuitry (MBIST and EDT controllers) perform dual functions: their original testing function and the additional function of state clearing for security. The MBIST controller clears internal memory states while the EDT controller clears flip-flop states, eliminating the need for separate custom reset logic and reducing device complexity.
2Reliability
If custom reset logic is implemented to clear flip-flops and memory, then security is improved, but chip space is consumed
Solution Approach 1:
The patent reuses existing test circuitry (MBIST and EDT controllers) for dual purposes: original testing functions and security state clearing. This multi-functionality approach eliminates the need for additional dedicated reset logic circuitry, thereby conserving chip space while maintaining security requirements.
Solution Approach 2:
The patent merges the state clearing function with the existing test and scan circuitry. The MBIST controller and EDT controller are combined with security functions, integrating memory clearing and flip-flop clearing capabilities into the existing test architecture rather than adding separate components.
3Reliability
If manual clearing methods are used for each flip-flop and memory cell, then clearing completeness is improved, but productivity and time efficiency deteriorate
Solution Approach 1:
The patent implements self-service by enabling the MBIST and EDT controllers to automatically clear their respective memory and flip-flop states without manual intervention. The controllers autonomously write test patterns to clear internal states, significantly improving clearing efficiency and productivity while ensuring complete clearing through systematic coverage of all memory cells and flip-flops.
Solution Approach 2:
The patent applies preliminary action by using pre-defined test patterns stored in the MBIST and EDT controllers to clear internal states. These pre-programmed patterns are automatically applied to ensure complete clearing of all memory cells and flip-flops, achieving both clearing completeness and high efficiency without manual configuration.
Data Source
AI summary
Systems and methods for state clearing of internal memory and flip-flops of a system using built-in test and scan circuitry are provided. A method includes a security processor: (1) fetching memory built-in self-test (MBIST) data and providing the MBIST data to an internal field-test (IFT) controller such that the IFT controller can drive the MBIST data via an IJTAG network to respective MBIST controllers, and (2) fetching scan data and providing the scan data to the IFT controller such that the IFT controller can drive the scan data via a scan network to respective embedded deterministic test (EDT) controllers. The method further includes each of the respective MBIST controllers state clearing respective internal memories by writing pertinent MBIST data into the respective internal memories. The method further includes each of the respective EDT controllers state clearing respective flip-flops by writing pertinent scan data into the respective flip-flops.