MBIST Scheduling Optimization for Memory Testing
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Solution Overview
Problem
Current methods for memory built-in-self-test (MBIST) in integrated circuits face challenges in optimizing power consumption, test time, area overhead, wire routing congestion, and interconnect timing, leading to potential chip damage and increased complexity, cost, and time to market due to the lack of suitable techniques for estimating these factors.
Innovation Solution
A method and apparatus for scheduling MBIST that involves assigning weights to scheduling parameters, calculating estimates using a compact model, and minimizing a cost function using optimization techniques like simulated annealing to generate an optimized schedule for testing memory devices, thereby optimizing power consumption, test time, area overhead, and wire routing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memories are tested in parallel to reduce test time, then productivity is improved, but power dissipation increases causing harmful thermal effects
Solution Approach 1:
The patent divides the memory testing process into multiple phases, where memories are tested in parallel during low-power phases and sequentially during high-power phases. This segmentation allows the system to achieve high productivity when safe to do so while preventing thermal damage during critical periods, resolving the contradiction between test time and power dissipation.
Solution Approach 2:
The patent implements dynamic testing scheduling where the test mode (parallel or serial) is adjusted based on real-time power consumption monitoring and thermal conditions. The system transitions between parallel and serial testing dynamically, allowing maximum productivity when thermal conditions permit and switching to serial testing when power dissipation approaches dangerous levels.
2Reliability
If MBIST hardware is added to enable testing, then reliability is improved, but device complexity and area overhead increase
Solution Approach 1:
The patent designs MBIST hardware that serves multiple functions: it can test different memory types (SRAM, DRAM, Flash), support various testing modes (parallel, serial, phased), and adapt to different chip configurations. This multi-functionality reduces the need for separate dedicated test circuits for each memory type, thereby reducing overall area overhead while maintaining comprehensive testing capability.
Solution Approach 2:
The patent uses configurable MBIST hardware parameters that can be adjusted based on the specific memory being tested and the desired test mode. By changing parameters such as test width, phase duration, and parallelism level, the same hardware can optimize its performance for different testing scenarios without requiring additional physical circuits, thus reducing area overhead.
3Measurement precision
If extensive CAD tools are used to estimate power and area parameters, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent pre-calculates and stores power consumption and area overhead estimates for various memory configurations and testing scenarios in lookup tables or databases during the design phase. During actual design, the system queries these pre-computed values rather than running extensive CAD simulations, achieving high measurement precision while dramatically reducing the time required for design iterations.
Solution Approach 2:
The patent creates simplified mathematical models and lookup tables that copy the essential characteristics of complex power and area calculations. These models replicate the behavior of full CAD tools but with much lower computational cost, allowing designers to obtain accurate estimates quickly without running time-consuming simulations for each design change.
Data Source
AI summary
Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results.