MC-CSD Re-sampler for Reduced Power and Complexity
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Solution Overview
Problem
Current re-samplers in signal chain systems, such as those used in communications transceivers and automotive radar receivers, face challenges with high power consumption and complexity, particularly at high sampling rates like 750 MHz, and are not efficiently supported by current semiconductor technology, necessitating parallelization to reduce power and area usage.
Innovation Solution
The implementation of multi-coefficient canonical-signed-digit (MC-CSD) multipliers and commutators in re-samplers, which replace standard multiplication operations with shift, addition, and subtraction, and utilize commutators to halve circuit area, allowing for parallel processing and reduced power consumption by clock gating and data gating unused components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If standard multiplication operations are used in re-samplers, then computational accuracy is maintained, but power consumption and circuit complexity increase significantly
Solution Approach 1:
The patent transforms multiplication operations into addition and subtraction operations by using Canonical Signed Digit (CSD) coefficients. This parameter change in the mathematical operation domain reduces the complexity of hardware implementation while maintaining computational accuracy, as addition and subtraction require simpler circuitry compared to multiplication.
Solution Approach 2:
The patent replaces the mechanical multiplication operation with a combination of shift operations and addition/subtraction operations. This substitution eliminates the need for complex multiplication circuits while achieving the same filtering function through a sequence of simpler operations.
2Use of energy by moving object
If parallelization is implemented to reduce power consumption, then power usage decreases, but device complexity increases
Solution Approach 1:
The patent divides the re-sampler into multiple parallel processing channels, each handling a portion of the computation. This segmentation allows power gating of inactive channels, reducing overall power consumption while distributing the computational load across multiple simpler units rather than one complex unit.
Solution Approach 2:
The patent employs periodic clock gating and data gating to activate only the necessary processing channels at specific time intervals. This periodic activation pattern reduces average power consumption by keeping idle channels in a low-power state while maintaining the ability to process all required data.
3Speed
If high sampling rates are used, then signal processing performance is improved, but power consumption and area usage increase
Solution Approach 1:
The patent changes the operational parameters of the arithmetic operations from multiplication to addition/subtraction with CSD coefficients. This parameter change enables high sampling rates to be achieved with reduced power consumption, as the simpler operations can be executed faster and with less energy per operation.
Solution Approach 2:
The patent segments the high-rate processing into multiple parallel lower-complexity channels that can operate at high sampling rates with reduced power per channel, achieving overall high performance while controlling total power consumption.
Data Source
AI summary
A re-sampler comprises a first CSD multiplier configured to receive input samples, a first accumulator coupled to the first CSD multiplier and configured to form a first MAC unit with the first CSD multiplier, a second CSD multiplier configured to receive the input samples, and a second accumulator coupled to the second CSD multiplier and configured to form a second MAC unit with the second CSD multiplier, wherein the re-sampler is configured to generate output samples based on the input samples. A method comprises receiving, by a first CSD multiplier, input samples, receiving, by a second CSD multiplier, the input samples, generating coefficients, scaling, using the first CSD multiplier and the second CSD multiplier, the input samples with coefficient vectors associated with the coefficients to form coefficient vector scaled input samples, and generating output samples based on the coefficient vector scaled input samples. The CSD multipliers may be MC-CSD multipliers.