Loop Detection in Multi-Chassis Link Aggregation

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Solution Overview

Problem

Existing network systems face resource-intensive methods for loop detection in multi-chassis link aggregation groups, leading to inefficient resource usage and potential data loss when loops occur.

Innovation Solution

A multi-chassis link aggregation group network device generates and sends untagged and tagged data units to detect loops, disabling affected ports and sending notifications to peers to prevent loop propagation, thereby efficiently managing network loops without blocking all ports or discarding data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If resource-intensive protocols like STP are used for loop detection, then loop detection capability is improved, but network and device resource consumption increases significantly

Engineering Contradiction:
Improveloop detection capabilityVSAvoidnetwork and device resource consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the parameters of loop detection by using lightweight OAM packets with specific VLAN tagging instead of heavy STP protocols. The detection mechanism uses modified Ethernet packets with source and destination MAC addresses that enable loop detection through simple comparison, reducing computational and bandwidth resources required while maintaining detection effectiveness

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs disposable OAM (Operations, Administration, and Maintenance) packets for loop detection instead of maintaining complex persistent protocol states. These packets are sent periodically and discarded after use, providing a low-cost, lightweight detection mechanism that consumes minimal network and device resources compared to traditional protocols

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Reliability

If all ports are blocked when a loop is detected, then loop propagation is prevented, but data packet loss occurs even for packets that should be forwarded

Engineering Contradiction:
Improveloop preventionVSAvoiddata packet loss
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The patent applies local quality by selectively disabling only the specific port where the loop is detected rather than blocking all ports. When a port receives a looped OAM packet, only that individual port is disabled, allowing other ports to continue forwarding legitimate data traffic normally, thus preventing unnecessary data loss while still containing the loop

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the loop containment action to affect only the local port involved in the loop rather than the entire network device. This granular approach isolates the problem to the specific faulty connection while preserving network-wide connectivity and data flow through other healthy ports

Inventive Principle:
Principle #1Segmentation

3Productivity

If ports remain active during loop detection, then data forwarding continues, but network resources are wasted processing looped data units

Engineering Contradiction:
Improvedata forwarding continuityVSAvoidresource waste from processing looped packets
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent converts the harmful effect of looped packets into a beneficial detection mechanism. By intentionally sending OAM packets through the network and monitoring for their return, the system uses the presence of looped traffic as a positive signal to identify and disable problematic ports, transforming what would normally be wasted resources into useful loop detection information

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS10778567B1Method and procedure for loop detection in multi-chassis link aggregation group (MCLAG) deployment within a communications system
Publication Date: 2020.09.15 JUNIPER NETWORKS INC
  • US10778567B1 patent drawing
  • US10778567B1 patent drawing
  • US10778567B1 patent drawing

AI summary

Apparatus and methods described herein relate to an apparatus including a set of ports and a processor operatively coupled to each port of the set of ports. A port from the set of ports can be associated with a port of a multi-chassis aggregate (MCAE) interface and a virtual local area network (VLAN). The processor can generate an untagged data unit and tagged data units. The processor can send the untagged data unit and the tagged data units via the port from the set of ports, and can receive a tagged data unit included in the tagged data units, and/or the untagged data unit. The processor can also forward the received data unit to a destination network peer when the received tagged data unit is associated with the VLAN, and can disable the port of the MCAE interface in response to the port from the set of ports receiving the data unit, when the received data unit is associated with the VLAN.