Multi-chip Module With In-Memory Processing Circuitry
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Solution Overview
Problem
Traditional chiplet architectures face latency issues due to the need for data to be processed in one memory space, then returned or sent to another memory space for further processing by multiple chips.
Innovation Solution
A multi-chip module (MCM) architecture that includes a common substrate with interconnected IC chips and a memory device equipped with in-memory processing circuitry, such as a co-processor or NoC circuitry, to manage transactions between the memory and the IC chips, reducing latency and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional chiplet architectures are used with dedicated memory spaces for each chip, then each chip can access its own memory independently, but data processing latency increases due to the need to return or send data between memory spaces
Solution Approach 1:
The patent merges multiple dedicated memory spaces into a single shared memory space that is accessible by multiple IC chips. This consolidation eliminates the need for data to be returned or sent between separate memory spaces, thereby reducing processing latency while simplifying memory management architecture.
Solution Approach 2:
The shared memory space serves multiple functions by being accessible to multiple IC chips simultaneously. Instead of each chip having its own dedicated memory space, the universal memory space can be accessed by any chip, enabling efficient data sharing and processing across the system.
2Loss of time
If multiple IC chips access a shared memory space with in-memory processing circuitry, then data processing latency is reduced, but the complexity of managing concurrent access and transactions increases
Solution Approach 1:
The in-memory processing circuitry acts as an intermediary between multiple IC chips and the shared memory space. It manages concurrent access requests, handles transactions, and coordinates data flow between chips and memory, thereby reducing access latency while preventing management complexity from escalating.
Solution Approach 2:
The in-memory processing circuitry provides self-service capabilities by autonomously managing memory transactions, arbitration, and data processing tasks. This self-managing approach reduces the burden on external controllers and simplifies the overall system architecture despite multiple concurrent accessors.
Data Source
AI summary
Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a chiplet-based multi-chip module (MCM) is disclosed. The chiplet-based MCM includes a package substrate and a first processing integrated circuit (IC) chiplet disposed on the package substrate. A second processing IC chiplet is disposed on the package substrate. At least one first row multi-port memory chiplet is disposed on the package substrate and coupled between the first processing IC chiplet and the second IC processing chiplet. Data transfers between the first processing IC chiplet and a destination IC chiplet are routed through the at least one first row multi-port memory chiplet.