Multi-Chip Module Interconnection via Interposer Substrate

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Solution Overview

Problem

Current techniques for interconnecting multiple integrated circuit dies face challenges such as interconnect issues and interference, limiting the ability to combine various functionalities on a single die effectively.

Innovation Solution

The solution involves packaging two integrated circuit dies, with one die acting as a primary and the other as a secondary, connected through an intermediate substrate, where the secondary die's core is disabled or in a reduced power mode, allowing the primary die to access its resources as if they were on the same die, using a common system interconnect protocol and address translation for optimized resource utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple integrated circuit dies are interconnected to form a single packaged device, then memory capacity and functionality are increased, but interconnect issues and interference problems arise

Engineering Contradiction:
Improvememory capacityVSAvoidinterconnect reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent uses an intermediate substrate as a mediator between multiple integrated circuit dies. This substrate provides a standardized interconnection interface that reduces direct die-to-die coupling, thereby minimizing interference issues while enabling increased memory capacity and functionality through multiple die integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the integrated circuit functionality across multiple separate dies that are then interconnected. By dividing the system into discrete functional blocks on separate dies, the design can optimize each die for specific functions while using the intermediate substrate to manage interconnections, reducing the complexity and interference of direct multi-die integration.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If multiple different types of die are combined to achieve common functionalities, then device versatility is improved, but manufacturing process compatibility becomes more difficult

Engineering Contradiction:
Improvedevice versatilityVSAvoidmanufacturing process compatibility
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The intermediate substrate provides a universal interconnection platform that can accommodate multiple different types of integrated circuit dies. This universal interface allows diverse die types (logic, RF, memory, etc.) to be combined in a single package without requiring process compatibility between all die types, as each die can be manufactured using its optimal process and then interconnected through the standardized substrate interface.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If various functionalities are combined on a single die, then device integration is improved, but manufacturing complexity and interference issues increase

Engineering Contradiction:
Improvedevice integrationVSAvoidinterference
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The patent segments different functional blocks (logic, RF, memory, etc.) onto separate dies rather than integrating them all on a single die. This segmentation maintains high device integration at the package level while reducing manufacturing complexity and interference issues by allowing each die to be optimized for its specific function with appropriate process techniques and physical layouts.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7827336B2Technique for interconnecting integrated circuits
Publication Date: 2010.11.02 NXP USA INC
  • US7827336B2 patent drawing
  • US7827336B2 patent drawing
  • US7827336B2 patent drawing

AI summary

Two integrated circuit die each having a processing core and on-board memory are interconnected and packaged together to form a multi-chip module. The first die is considered primary and the second die is considered secondary are connected through an interposer. The first and second die may be the same design and thus have the same resources such as peripherals and memory and preferably have a common system interconnect protocol. The core of the second die is disabled or at least placed in a reduced power mode. The first die includes minimal circuit for interconnecting to the second die. The second die has some required interface circuitry and an address translator. The result is that the core of the first die can perform transactions with the memory and other resources of the second integrated circuit as if the memory and other resources were on the first die.