Multi-Chip Module Redundancy for Fault-Tolerant HPC Interconnects
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Solution Overview
Problem
High-performance computing (HPC) systems face challenges in achieving high reliability, availability, and serviceability (RAS) due to increased complexity and failure modes in multi-chip modules (MCMs) with hundreds of thousands of interconnected processors, leading to higher failure-in-time (FIT) rates and downtime.
Innovation Solution
The implementation of a multi-chip module (MCM) with global and local redundancy, where redundant sites, chips, and components are in a standby mode until failures are detected, using control logic and telemetry-monitoring mechanisms to transition them to an operating mode, maintaining a fully connected, non-blocking topology and preserving communication efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are integrated into an MCM to increase computational density and performance, then processing power and throughput are improved, but the complexity of the system increases and failure rates increase
Solution Approach 1:
The MCM is divided into multiple independent sites, each containing a subset of chips and components. This segmentation isolates failures to specific sites rather than affecting the entire system, and allows individual sites to be managed independently with their own redundancy mechanisms.
Solution Approach 2:
Different levels of redundancy are applied at different hierarchical levels: site-level redundancy provides global backup capacity, while component-level redundancy within each site provides local backup. This differentiated approach optimizes reliability without uniformly increasing complexity across the entire system.
2Reliability
If redundant components are added to provide fault tolerance, then system reliability is improved, but device complexity and FIT rates increase
Solution Approach 1:
Redundant sites and components are pre-configured in standby mode before failures occur. The control logic continuously monitors system health and automatically activates redundant elements only when failures are detected, avoiding the complexity of managing continuously active redundant components while ensuring immediate failover capability.
Solution Approach 2:
The system implements partial redundancy by providing backup capacity at the site level rather than requiring complete component-level redundancy for every element. This approach provides sufficient fault tolerance for HPC workloads while avoiding the excessive complexity and cost of full system redundancy.
3Loss of time
If standby redundant components are implemented, then downtime is reduced through seamless failover, but device complexity increases due to monitoring and switching mechanisms
Solution Approach 1:
The control logic continuously monitors the operational status of all sites and components through telemetry data and performance metrics. This feedback mechanism enables automatic detection of failures and triggers seamless switching to redundant elements, minimizing downtime while keeping the control mechanism relatively simple through rule-based decision making.
Solution Approach 2:
The MCM system performs self-diagnosis and self-recovery by automatically detecting failures through monitored parameters and activating redundant components without external intervention. This self-service capability reduces downtime while avoiding the complexity of external monitoring and manual switching systems.
Data Source
AI summary
A multi-chip module (MCM) is described. This MCM includes multiple sites, where a given site in the multiple sites includes multiple chips with proximity connectors that communicate information through proximity communication within the MCM via multiple components associated with the given site. Note that the MCM includes global redundancy and local redundancy at the given site. In particular, the global redundancy involves providing one or more redundant sites in the multiple sites. Furthermore, the local redundancy involves providing one or more redundant chips in the multiple chips and one or more redundant components in the multiple components.