MCM SerDes Lane Sampling Using Shared Phase Detector Commands
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Solution Overview
Problem
In Multi-Chip-Modules (MCMs), conventional Clock-Data-Recovery (CDR) circuits are power-consuming and complex, especially when multiple lanes are implemented, leading to significant additional power and area requirements.
Innovation Solution
The implementation of a Multi-Chip-Module (MCM) with a clock-data recovery circuit (CDR) and data samplers, where the CDR restores data and clock from one lane and outputs phase correction signaling, allowing data samplers to sample other lanes based on this signaling, reducing the need for full CDRs on all lanes and enabling power and area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full CDR circuits are implemented on all lanes, then clock and data recovery reliability is improved, but power consumption and area usage increase significantly
Solution Approach 1:
The system segments the CDR functionality by identifying that only one lane requires a full CDR circuit while other lanes can use simplified sampler circuits. This segmentation allows the majority of lanes to use low-power samplers while maintaining overall system reliability through the master CDR's phase correction signaling.
Solution Approach 2:
The master CDR circuit performs multiple functions: it recovers clock and data from its lane, generates phase correction signals, and provides timing reference for all other lanes through the sampler circuits. This multi-functionality eliminates the need for separate full CDR circuits on each lane.
2Reliability
If full CDR circuits are implemented on all lanes, then clock and data recovery reliability is improved, but area usage increases significantly
Solution Approach 1:
The system segments the CDR functionality by identifying that only one lane requires a full CDR circuit while other lanes can use simplified sampler circuits. This segmentation allows the majority of lanes to use low-power samplers while maintaining overall system reliability through the master CDR's phase correction signaling.
Solution Approach 2:
The master CDR circuit performs multiple functions: it recovers clock and data from its lane, generates phase correction signals, and provides timing reference for all other lanes through the sampler circuits. This multi-functionality eliminates the need for separate full CDR circuits on each lane.
3Use of energy by moving object
If simplified samplers are used on all lanes, then power consumption and area usage are reduced, but phase synchronization accuracy deteriorates
Solution Approach 1:
Phase correction signals act as intermediaries that transfer timing information from the master CDR to the sampler circuits. These signals enable the simplified samplers to achieve accurate phase synchronization without requiring full CDR functionality, thus maintaining precision while reducing power consumption.
Solution Approach 2:
The system implements feedback through phase correction signals that continuously adjust the sampler timing based on the master CDR's phase detection. This feedback mechanism ensures that even simplified samplers maintain accurate phase synchronization with the clock signal.
Data Source
AI summary
A Multi-Chip-Module (MCM) includes an MCM substrate, and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus including at least first and second embedded-clock data lanes. The DCIC includes a clock-data recovery circuit (CDR) and a data sampler. The CDR is configured to restore a data and a clock from the first data lane, and to output phase correction signaling. The data sampler is configured to restore the data from the second data lane by sampling the second data lane at a phase responsive to the phase correction signaling derived from the first data lane.