Multi-Chip Module Unified Memory Architecture for Low-Latency Access
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Solution Overview
Problem
As integrated circuit chips become larger, manufacturing yields decrease, leading to increased costs, and traditional chiplet architectures often result in significant latency when accessing memory due to separate memory spaces for different chips.
Innovation Solution
A multi-chip module (MCM) architecture with a unified memory space accessible by multiple IC chips, utilizing a logic base die with in-memory processing circuitry and network-on-chip (NoC) circuitry to facilitate efficient data access and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional chiplet architectures with dedicated memory spaces are used, then each chip can access its own memory independently, but data transfer latency between chips increases significantly
Solution Approach 1:
The patent merges separate memory spaces into a unified shared memory space accessible by multiple chiplets. The memory device is configured with a unified memory space that can be accessed by any chiplet in the MCM, eliminating the need for data to be transferred back and forth between dedicated memory spaces. This is achieved through a memory interface that routes access requests from any chiplet to any location in the unified memory space.
Solution Approach 2:
The memory device is designed with multi-functionality to serve multiple chiplets simultaneously. The memory interface can handle access requests from multiple chiplets and route them to appropriate locations in the unified memory space. The system supports both unified memory mode and dedicated memory mode, providing universal compatibility with different access patterns and requirements.
2Loss of time
If a unified memory space is implemented, then data transfer latency is reduced and power efficiency improves, but memory access control complexity increases
Solution Approach 1:
The patent introduces a memory interface as an intermediary between chiplets and the unified memory space. This interface handles address translation, access arbitration, and data routing, shielding chiplets from the complexity of unified memory management. The interface includes control logic that receives access requests from chiplets and translates them into appropriate memory access operations.
Solution Approach 2:
The patent adds a memory management dimension to the chiplet architecture by introducing control circuitry that operates at the memory interface level. This allows memory access control functions to be separated from individual chiplets and centralized in the memory device, enabling unified memory management without increasing chiplet complexity.
3Quantity of substance
If memory capacity is increased to meet growing data needs, then system functionality improves, but physical I/O space requirements increase
Solution Approach 1:
The patent implements a nested memory architecture where additional memory devices can be stacked or coupled to existing memory devices. The memory device includes interfaces that allow daisy-chaining or stacking of additional memory devices, enabling memory capacity expansion without requiring additional external I/O connections. Each memory device can be accessed through the unified memory interface.
Data Source
AI summary
Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, an integrated circuit (IC) base die is disclosed. The IC base die is configured to couple to a stack of memory die and includes a first port including a die-to-die (D2D) interface to couple to an IC device. A second port includes a memory interface to access a memory other than the stack of memory die. Memory control circuitry controls memory access operations directed to the memory other than the stack of memory die.