Multi-Chip Package Cavities Eliminate Bonding Wires
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Solution Overview
Problem
Conventional multi-chip package structures are not amenable to miniaturization, leading to increased thickness and dimensions, which hampers their competitiveness and demands for reduced size in semiconductor packages.
Innovation Solution
A method involving the formation of cavities on a first wafer to create conductive walls that connect to a metal layer, allowing for the elimination of bonding wires and simplification of the circuit layout by stacking wafers face-to-face, thereby reducing the overall thickness and dimension of the package structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional multi-chip package structure with bonding wires is used, then electrical connection between chips and carrier is achieved, but the overall thickness and dimension of the package structure increase
Solution Approach 1:
The patent extracts and removes the bonding wires from the package structure, replacing them with direct conductive connections formed through cavities in the carrier substrate. This elimination of external bonding wires directly reduces the package thickness and dimension while simplifying the overall structure.
Solution Approach 2:
The patent transitions from a planar circuit layout using bonding wires to a three-dimensional structure with conductive walls formed within cavities. The conductive connections are created by forming conductive patterns on the inner walls of cavities, enabling vertical and lateral electrical connections without requiring external wire bonds, thus reducing the package footprint and thickness.
2Area of stationary object
If bonding wires are used for electrical connection, then signal transmission between chips and carrier is enabled, but the package structure becomes larger in dimension
Solution Approach 1:
The patent merges the functions of the carrier substrate, bonding wires, and connection pads into an integrated structure. The conductive walls formed within the cavities simultaneously provide mechanical support, electrical connection, and signal transmission functions that were previously separated into distinct components, thereby reducing the overall package dimension.
Solution Approach 2:
The patent performs preliminary actions by pre-forming cavities and conductive wall patterns on the carrier substrate before chip mounting. This allows the conductive connection paths to be established in advance, eliminating the need for subsequent wire bonding operations and reducing the overall manufacturing complexity despite the added precision requirements in earlier steps.
3Manufacturing precision
If conventional package structure is used, then chip mounting is achieved, but miniaturization demands cannot be met
Solution Approach 1:
The patent segments the carrier substrate into multiple regions with cavities formed at specific locations. Each cavity contains conductive walls that provide localized electrical connections, allowing the package structure to be divided into functional zones. This segmentation enables precise control over connection points and facilitates miniaturization by eliminating the need for extensive external wiring.
Solution Approach 2:
The patent implements a nested structure where conductive walls are formed within cavities that are themselves formed within the carrier substrate. The chips are mounted on the carrier and electrically connected through the nested cavity-conductive wall-p chip configuration, creating a compact, space-efficient structure that enables miniaturization while maintaining electrical connectivity.
Data Source
AI summary
A method of fabricating a multi-chip package structure is provided. In the method, a number of cavities are formed on a predetermined cutting line of a first wafer by partly removing the first wafer and a first metal layer. Conductive walls of a first circuit layer are electrically connected to a cut cross-section of the first metal layer exposed by the cavities. In addition, conductive bumps of a second wafer or a chip are pressed into a cover layer and electrically connected to the first circuit layer. The first metal layer is then patterned to form a second circuit layer having a number of second pads. Next, the first wafer and the second wafer are cut along the predetermined cutting line to form a number of separated multi-chip package structures.