Multi-Chip Package Chip Select Logic Circuit
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Solution Overview
Problem
Multi-chip packages face challenges in efficiently selecting and managing multiple memory devices using a single external chip select signal, as existing solutions lack flexibility in device identification and memory management, particularly in handling faulty devices and memory segment reassignment.
Innovation Solution
The implementation of a multi-chip package with chip select logic circuits that generate individual internal chip selects for each memory device based on an external chip select signal and device identification, allowing for flexible device selection, reprogramming of device IDs, and memory segment reassignment, including diagnostic modes for handling faulty devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple memory devices are integrated into a single multi-chip package, then the package footprint on the PCB is reduced and device integration is improved, but the complexity of selecting and managing individual devices within the package increases
Solution Approach 1:
The patent divides the package into multiple independently selectable memory devices, each with its own device ID. The chip select logic circuit segments the single external chip select signal into multiple internal chip select signals by comparing address bits with device IDs, allowing individual device selection without increasing external footprint.
Solution Approach 2:
The patent introduces a chip select logic circuit as an intermediary component that receives the external chip select signal and address bits, then generates appropriate internal chip select signals for specific memory devices. This mediator resolves the complexity by automating the device selection process based on device ID matching.
2Quantity of substance
If a single external chip select signal is used for multiple memory devices, then the number of external pins is reduced, but the flexibility in device identification and memory management is limited
Solution Approach 1:
The patent adds a new dimension of device identification by introducing multi-bit device IDs and address bit comparisons. Instead of using multiple external chip select pins (one dimension), the system uses a single pin combined with address bit matching (adding another dimension of control), thereby reducing pin count while maintaining flexibility.
Solution Approach 2:
The patent changes the parameters used for device selection from simple pin activation to multi-bit device ID matching. By comparing address bits with stored device IDs, the system achieves flexible device identification and memory management using a single external chip select signal.
3Reliability
If device IDs are hard-coded during manufacturing, then device identification is reliable, but the ability to reassign memory segments and handle faulty devices is reduced
Solution Approach 1:
The patent makes the device ID assignment dynamic by allowing reconfiguration of the chip select logic circuit. Device IDs can be programmed or reprogrammed after manufacturing, enabling memory segment reassignment and faulty device handling while maintaining reliable identification through the matching mechanism.
Data Source
AI summary
Embodiments of the invention may generally provide techniques that allow a single externally supplied chip select signal to be used to independently select a plurality of devices in a multi-chip package (MCP). For some embodiments, higher order address bits are compared to device IDs assigned to each device. An internally generated chip select line is asserted for a device having a match between the address bits and its device ID.