Multi-Chip Package Memory Repair Control Method
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Solution Overview
Problem
Multi-chip package memory devices face challenges in efficiently replacing failed memory chips without disrupting the operation of other functional chips, leading to potential data loss and reduced storage capacity.
Innovation Solution
A control method that applies stack signals and repair signals to memory dies to identify and replace failed chips, utilizing repaired memory dies by altering the repair signal levels and stack states, allowing seamless substitution without interrupting the logical access order of other non-failed memory dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a failed memory chip is replaced in a multi-chip package memory device, then the reliability of the memory device is improved, but the complexity of the control system increases due to the need to manage repair signals and stack states
Solution Approach 1:
The memory device is divided into multiple independent memory dies, each with its own repair pads and stack pads. This segmentation allows individual replacement of failed chips while maintaining control over the entire system through unified signal management, resolving the contradiction between reliability improvement and control complexity
Solution Approach 2:
Repair signals are introduced as intermediary signals that mediate between the control logic and memory dies. These signals enable the control logic to identify and activate repaired memory dies without requiring complex direct control mechanisms, thus improving reliability while managing control system complexity
2Quantity of substance
If repaired memory dies are activated to replace failed ones, then the storage capacity is maintained, but the difficulty of detecting and measuring the operational state increases due to multiple stack states and repair signal levels
Solution Approach 1:
The system uses different voltage levels of repair signals (first level indicating non-repaired state, second level indicating repaired state) analogous to color changes for visual indication. This encoding scheme allows the operational state of each memory die to be easily detected and measured through simple voltage level detection, maintaining storage capacity while reducing detection difficulty
Solution Approach 2:
Stack information from failed memory dies is copied to repaired memory dies, including access order and operational parameters. This copying mechanism ensures that the repaired dies seamlessly replace the failed ones, maintaining storage capacity and logical access order while simplifying state detection through standardized information transfer
3Stability of the object's composition
If stack information is stored and transferred between memory dies, then the logical access order is preserved, but the loss of time increases due to the additional steps of storing and retrieving stack information
Solution Approach 1:
Stack information is pre-stored in each memory die's internal memory during manufacturing or initialization. When a memory die is repaired and activated, the required stack information is already available locally, eliminating the need for time-consuming retrieval and transfer operations. This preliminary action preserves logical access order stability while minimizing time loss
Solution Approach 2:
The patent replaces physical movement or complex mechanical transfer mechanisms with electronic signal-based information transfer. Stack information is transferred through electrical signals between memory dies and control logic, significantly reducing transfer time compared to mechanical systems while maintaining the stability of logical access order
Data Source
AI summary
A control method of a multi-chip package memory device includes the steps of applying stack signals to stack pads of memory dies, applying a repair signal to repair pads of the respective memory dies, setting one or more repaired memory dies for replacing a failed memory die among the memory dies, based on the repair signal applied to the respective memory dies, and setting stack states indicating a logical access order of the other memory dies excluding the repaired memory die, based on the stack signals applied to the other memory dies.