MCP Parallel Chip Testing for Early Crack Defect Detection
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Solution Overview
Problem
In multi-chip packages (MCPs) used in semiconductor devices, crack defects in second type semiconductor chips are often identified only after testing the first type semiconductor chip, leading to decreased productivity in MCP testing.
Innovation Solution
A test method is developed to determine if a crack defect exists in a second type semiconductor chip during the testing of a first type semiconductor chip in an MCP. This is achieved by performing a function test on the first type semiconductor chip and a low power mode test on the second type semiconductor chip in parallel, using separate channel terminals, and analyzing the current measured in the second channel terminals to detect any crack defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a function test is performed on the first type semiconductor chip, then the functionality of the first type chip is verified, but crack defects in the second type semiconductor chip cannot be detected until after the first type chip test is completed
Solution Approach 1:
The test process is segmented into two independent parallel tests: a function test for the first type semiconductor chip and a low power mode test for the second type semiconductor chip. Each test uses separate channel terminals and operates independently, allowing both tests to be conducted simultaneously without interference, thus enabling crack defect detection in the second type chip during the function test of the first type chip.
Solution Approach 2:
The low power mode test is performed in advance during the function test of the first type chip, rather than waiting until after the function test completes. By conducting the crack defect detection test preliminarily and in parallel, the overall test time is reduced while maintaining detection accuracy.
2Measurement precision
If sequential testing of first type and second type semiconductor chips is performed, then each chip can be tested thoroughly, but productivity decreases due to inability to detect crack defects in second type chip until after first type chip test
Solution Approach 1:
Two separate test processes (function test for first type chip and low power mode test for second type chip) are merged into a single parallel execution framework. Both tests share the same test equipment and time resources, conducted simultaneously through separate channel terminals, thus maintaining test completeness while doubling productivity.
Solution Approach 2:
The test equipment maintains continuous useful action by performing both function test and low power mode test simultaneously without idle time. While the first type chip undergoes function testing, the second type chip concurrently undergoes crack defect detection, eliminating the sequential waiting period and maximizing equipment utilization.
3Productivity
If separate channel terminals are used for function test and low power mode test, then parallel testing can be performed, but device complexity increases
Solution Approach 1:
The test equipment is designed with multi-functionality, where channel terminals can serve dual purposes: conducting function tests on first type semiconductor chips and low power mode tests on second type semiconductor chips. This universal design allows parallel testing capabilities without requiring entirely separate dedicated test systems for each test type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method allows for the simultaneous testing of both types of semiconductor chips, enabling early detection of crack defects in the second type semiconductor chip, thus improving test efficiency and productivity.
Implementation Method 1
the test host applies signals related to the function test of the first type semiconductor chip to the first channel terminals... and applies signals related to the low power mode test of the second type semiconductor chip to the second channel terminals... analyzing a current measured in the second channel terminals
Data Source
AI summary
A method of manufacturing a multi-chip package (MCP) is provided. The MCP includes a first type semiconductor chip, a second type semiconductor chip, and a memory controller configured to control the second type semiconductor chip. The method includes mounting the first type semiconductor chip and the memory controller on a substrate, mounting the second type semiconductor chip on the first type semiconductor chip, forming a mold layer to cover the first and second type semiconductor chips and the memory controller, performing a function test on the first type semiconductor chip and simultaneously determining whether a crack defect occurred in the second type semiconductor chip. The crack defect of the second type semiconductor chip is determined when a current measured in a low power mode test of the second type semiconductor chip is greater than or equal to a test reference value.