Multichip Package Link Error Detection Across Protocol Streams
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Solution Overview
Problem
As computing systems become more complex, existing interconnect architectures face challenges in meeting bandwidth requirements and managing power consumption efficiently, particularly in high-performance server environments and mobile devices, where traditional solutions are either performance-oriented or power-saving, but not both simultaneously.
Innovation Solution
The development of a multichip package link (MCPL) that employs a physical layer with electrical and logical components to provide a high-bandwidth, low-power, and low-latency interface, supporting multiple protocols and featuring regulated mid-rail termination, active crosstalk cancellation, and error detection mechanisms, enabling efficient communication between multiple chips within a package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional multi-drop buses are used for interconnect, then device complexity is reduced, but bandwidth and communication performance deteriorate
Solution Approach 1:
The patent segments the traditional multi-drop bus into multiple point-to-point links, each connecting specific devices. This segmentation allows dedicated communication paths that support higher bandwidth while maintaining manageable complexity through modular link design.
Solution Approach 2:
The patent transitions from a single shared bus dimension to multiple parallel point-to-point link dimensions. This dimensional expansion enables simultaneous communications across multiple device pairs, dramatically increasing aggregate bandwidth without proportionally increasing complexity.
2Productivity
If multiple physical processors (sockets) are added to increase computing power, then processing capability improves, but communication requirements and system complexity increase
Solution Approach 1:
The patent implements a universal interconnect architecture where the same point-to-point link technology serves multiple communication purposes: processor-to-processor communication, processor-to-memory access, and inter-chip data transfer. This multi-functionality supports scaling to multiple sockets without requiring socket-specific communication solutions.
3Speed
If data rate is increased to meet bandwidth demand, then communication speed improves, but power consumption increases
Solution Approach 1:
The patent implements dynamic power management where the interconnect can adjust its operating characteristics based on actual communication needs. The system can operate at high data rates when full bandwidth is required and reduce power consumption during lower-demand periods through state transitions and selective activation of communication paths.
Data Source
AI summary
First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.