MCSP Power Semiconductor Device Thickness Reduction
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Solution Overview
Problem
Conventional molded chip-scale package (MCSP) power semiconductor devices face challenges such as high manufacturing costs, increased thickness due to lead frames, and difficulties in reducing on-resistance and marking issues with thin metal layers, which are not true chip-scale packages and are prone to deformation and surface roughness.
Innovation Solution
The method involves forming a molding layer over semiconductor chips, implanting metal bumps, and using a metal foil layer and composite tape to reduce thickness and enhance electrical conductivity, eliminating the need for lead frames and improving marking durability by using a conductive adhesive layer and laminating a metal foil layer with a composite tape that includes an adhesive and protective film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a lead frame is used in the packaging structure, then the mechanical strength and clamping pressure resistance are improved, but the manufacturing cost and device thickness increase
Solution Approach 1:
The patent removes the lead frame from the packaging structure entirely, extracting the problematic component that caused both increased thickness and manufacturing complexity. The chip is directly mounted on the substrate without requiring a lead frame, thereby reducing device thickness while eliminating the source of manufacturing cost increases
Solution Approach 2:
The substrate serves multiple functions: it provides mechanical support, electrical connections, and mounting surface for the chip. By making the substrate multi-functional, the patent eliminates the need for separate lead frame components, reducing overall device thickness while maintaining structural integrity
2Length of stationary object
If a thin metal layer is deposited on the back of the chip, then the chip scale packaging is achieved, but the on-resistance and parasitic resistance cannot be reduced
Solution Approach 1:
Instead of relying on a thin metal layer on the chip back surface, the patent extends the low-resistance path into the third dimension by using thick copper pillars that protrude from the substrate. This vertical dimension provides a low-resistance electrical connection path that compensates for the reduced horizontal metal layer area
Solution Approach 2:
The patent uses a composite structure combining the chip, substrate, and copper pillars. The copper pillars provide excellent electrical conductivity and mechanical support, while the substrate provides additional conduction paths. This composite approach achieves low on-resistance without requiring a thick metal layer on the chip itself
3Length of stationary object
If the metal layer is exposed on the back of the chip, then the chip scale packaging is achieved, but the marking is difficult and prone to wear off
Solution Approach 1:
The patent introduces an intermediary layer (protective coating or adhesive layer) between the metal features and the marking surface. This intermediary layer provides a suitable surface for marking while protecting the underlying metal structure, making marking easier and more durable without compromising the chip-scale packaging
4Ease of manufacture
If a plastic layer is formed on the metal layer to enable marking, then the marking can be done by printing or etching, but the polishing and thinning create a rough surface with pits
Solution Approach 1:
The patent performs marking operations on the protective coating layer before the final polishing and thinning steps. By marking earlier in the process when the surface is still flat and accessible, the marking is completed before surface roughness is introduced by subsequent polishing operations
Solution Approach 2:
The protective coating serves as an intermediary marking surface that can be marked with high precision. This coating layer is then polished together with the chip, but the marking has already been transferred or etched into the coating, preserving the marking quality even after the surface is thinned and slightly roughened
Data Source
AI summary
The present invention discloses the MCSP power semiconductor device and the preparation method thereof. In the present invention method, a metal foil layer is attached to the back of the wafer using a conductive adhesive layer and a composite tape is laminated on the metal foil layer. Thus, individual MCSP power semiconductor devices are separated by cutting the wafer, the conductive adhesive, the metal foil layer and the composite tape along the scribe lines between adjacent semiconductor chips formed on the front of the wafer.