MCU Address Translation Layout for Hardware-Based ASLR
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Solution Overview
Problem
Implementing address space layout randomization (ASLR) in microcontroller units (MCUs) is challenging due to the large circuit size and memory requirements of virtual memory management functions, which complicates real-time processing and software design.
Innovation Solution
A control device with an MCU that includes a CPU, system bus, storage, and an address translator, which operates in a limitation release mode initially and switches to a limitation mode after startup, using a special function register to set and manage translation rules for addresses, enabling ASLR without parallel operation of additional software.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If virtual memory management function is implemented in MCU to achieve ASLR, then security against arbitrary-code execution attacks is improved, but circuit size and memory requirements increase significantly
Solution Approach 1:
The patent extracts the address translation function from the complex virtual memory management system and implements it directly in the address translator hardware component. This separation allows ASLR to be achieved without implementing the entire virtual memory management function, thereby reducing circuit size while maintaining security.
Solution Approach 2:
The patent uses preliminary action by embedding invalid addresses in advance in the application software at build time. The address translator then translates these invalid addresses to valid addresses at runtime, enabling ASLR without requiring complex parallel software operations.
2Reliability
If virtual memory management software operates in parallel with application software to achieve ASLR, then security is improved, but processing time estimation becomes complex and software design difficulty increases
Solution Approach 1:
The patent replaces the mechanical system of parallel software operations with a hardware-based address translation mechanism. The address translator operates autonomously in hardware, eliminating the need for complex parallel software management and simplifying both real-time processing estimation and software design.
3Reliability
If high-performance CPU is used to operate application software and virtual memory management software in parallel, then ASLR functionality is achieved, but cost increases
Solution Approach 1:
The patent implements self-service by enabling the address translator to autonomously perform address translation without requiring high-performance CPU resources. The system serves its own address translation needs through dedicated hardware, eliminating the need for expensive high-performance processors while maintaining security functionality.
Data Source
AI summary
A control device 10 includes an MCU 20 including a CPU 22, a system bus 26, storage 28, and an address translator 24 translating an address in the CPU address space of the CPU 22 to and from an address in the system bus address space of the system bus 26 according to the translation rule set in the special function register 24A. The MCU 20 starts up in the limitation-release mode in which all addresses in the CPU address space are available, and switches to the limitation mode in which only some of the addresses in the CPU address space are available when a predetermined condition is satisfied after the start-up. For the special function register 24A, the translation rule is settable and readable in the limitation release mode, and the translation rule is neither settable nor readable in the limitation mode.