MCU Mirrored Buffer Multiplexing for Faster Boot With Less SRAM
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Solution Overview
Problem
Conventional MCU chips with buffer-based solutions for speeding up operations increase on-chip SRAM requirements and chip cost, especially as they require larger buffers for higher performance, leading to inefficiencies and increased expenses.
Innovation Solution
A memory controller with a built-in mirrored buffer of smaller capacity than the NVM, time-division multiplexed to sequentially copy and override contents, allowing the CPU to directly access and execute from the mirrored buffer without waiting, reducing hardware overhead and chip cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a buffer is introduced into the MCU chip to speed up operation, then the reading and writing speed is improved, but the on-chip SRAM capacity increases and chip cost increases
Solution Approach 1:
The mirrored buffer is time-division multiplexed to serve multiple functions: it acts as a buffer for copying NVM contents during boot, and simultaneously serves as execution memory for the CPU. This multi-functional usage eliminates the need for separate dedicated buffer memory, reducing overall SRAM requirements while maintaining fast access performance.
Solution Approach 2:
The system dynamically switches the role of the mirrored buffer between different time periods - during boot phase it receives and stores data from NVM, during execution phase it provides fast access to the CPU. This dynamic time-division multiplexing allows the same hardware resource to adapt to different operational requirements, improving efficiency without increasing capacity.
2Productivity
If the buffer capacity is increased to support higher performance requirements, then the code execution capability is improved, but the chip cost increases further
Solution Approach 1:
The mirrored buffer operates in periodic cycles: first copying data from NVM in sequential steps, then releasing the CPU to execute from the buffer, while simultaneously initiating the next copying step. This periodic operation pattern allows the buffer to be reused efficiently across multiple code segments, supporting high productivity without requiring large capacity.
Solution Approach 2:
The system performs preliminary copying of code segments from NVM to the mirrored buffer before the CPU needs to execute them. This advance preparation ensures that when the CPU requires code execution, the data is already in fast memory, enabling high performance without requiring the buffer to hold all code simultaneously.
3Device complexity
If contents are copied sequentially from NVM to buffer, then the copying process is simplified, but the startup time increases
Solution Approach 1:
The copying process continues uninterrupted in the background while the CPU executes previously copied code. Instead of pausing CPU execution to complete copying, the system maintains continuous useful action by overlapping the copying of next code segments with the execution of current segments, reducing total startup time without complicating the copying mechanism.
Solution Approach 2:
The system periodically switches between copying mode and execution mode, with each copying step completed before the corresponding code segment is needed for execution. This periodic rhythm maintains simplicity in the copying process while minimizing delays through efficient timing and overlap with CPU execution activities.
Data Source
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AI summary
The present invention provides a memory controller and an MCU chip, in which a mirrored buffer with a small capacity built in the MCU can be time-division multiplexed as required by actual boot settings so that contents in the NVM are copied into the mirrored buffer at different times. Moreover, a CPU can read and run the copied contents in the mirrored buffer. Additionally, new contents are copied into the mirrored buffer during or after the CPU's execution of previously copied contents in such a manner that the newly copied contents can override part or the entirety of the previous contents. With this arrangement, compared with mirrored buffers employed in conventional MCUs, hardware overhead can be reduced and significant reductions in MCU chip cost can be achieved. Further, according to the present invention, after each POR or system reset of the MCU chip, reduced contents are copied into the mirrored buffer, compared with the prior art, significantly shortening the startup time of the system.