MCU Hardware Checksum Monitoring for Fast Register Integrity Checks

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional automotive microcontroller units face challenges in detecting bit flip errors in configuration registers within the stringent Fault Time Tolerance Interval (FTTI), as software-based detection procedures are inadequate for checking a high number of safety-critical registers within a short time frame without impacting performance.

Innovation Solution

A hardware monitoring module is integrated into the microcontroller unit, which autonomously reads configuration data, computes checksums, and compares them to expected values, triggering an alarm for mismatches, thereby providing an efficient error detection mechanism independent of software procedures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a software procedure running in the CPU is used to check configuration registers, then the detection mechanism is simple to implement, but the detection speed is too slow to meet the FTTI requirement of 1 ms when checking a high number of safety relevant registers

Engineering Contradiction:
Improveerror detection capabilityVSAvoiddetection speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent replaces the software-based detection mechanism (running in CPU) with a hardware-based monitoring module that operates independently. This hardware module includes dedicated circuitry for reading configuration memory locations, computing checksums, and comparing results, thereby substituting the mechanical/software process with a hardware system that achieves the required detection speed within the 1 ms FTTI while maintaining full error detection capability

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces a dedicated hardware monitoring module as an intermediary between the configuration memory locations and the error detection function. This module includes a checksum computation unit and a comparison unit that operate independently of the CPU, acting as an intermediary structure that专门 handles the error detection task with hardware-level speed while the CPU focuses on other processing tasks

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If a hardware monitoring module is introduced to achieve fast error detection, then the detection speed meets FTTI requirements, but the device complexity increases

Engineering Contradiction:
Improvedetection speedVSAvoidhardware structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the error detection function into distinct hardware components: a monitoring module with address register, data register, checksum computation unit, and comparison unit. Each component has a specific function, and they work together through defined interfaces. This segmentation allows the complex detection task to be divided into manageable hardware blocks that can be independently designed and optimized

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The hardware monitoring module is designed to autonomously perform the complete error detection sequence: it automatically reads from configuration memory locations, computes checksums using its dedicated computation unit, compares results with stored expected values, and generates error signals without CPU intervention. This self-service capability reduces the overall system complexity by making the detection function independent while meeting the 1 ms FTTI requirement

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12147209B2Microcontroller unit and corresponding method of operation
Publication Date: 2024.11.19 STMICROELECTRONICS SRL
  • US12147209B2 patent drawing
  • US12147209B2 patent drawing

AI summary

A set of configuration memory locations store configuration data for a microcontroller unit. A hardware monitoring module is coupled by an interconnection bus to the configuration memory locations. The hardware monitoring module reads from an instruction memory a command including an address of a target memory location in the set of configuration memory locations. Data is read from the target memory location corresponding to the address read and a checksum value is computed as a function of the data that is read from the target memory location. The computed checksum value is then compared to a respective expected checksum value stored in a checksum storage unit. An alarm signal is triggered in response to a mismatch detected between the computed checksum value and the respective expected checksum value.