MCU Comatose Mode with Regulator Shutdown and Stable I/O States
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Solution Overview
Problem
MCU chips face challenges in power conservation, as existing power-saving modes either lead to unknown digital output states when clocked off or require complete chip power-down, which can cause issues with interfacing and configuration states during low-power operations.
Innovation Solution
A microcontroller unit with a comatose mode that uses a voltage regulator to provide a zero-volt regulated output, allowing digital peripherals to maintain a known digital low state and latch the last state of digital control signals, ensuring stable output states during power-down and minimizing power loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the clock circuitry is halted to save power, then power consumption is reduced, but the digital output states become unknown
Solution Approach 1:
Before halting the clock circuitry to enter low-power mode, the patent latches the current digital output states into hold registers. This preliminary action ensures that when the clock is stopped, the output states are preserved and remain known, eliminating the uncertainty that would normally occur when clocking stops.
2Use of energy by moving object
If the complete chip is powered down to save power, then power consumption is minimized, but configuration information is lost and interfacing becomes problematic
Solution Approach 1:
The patent divides the chip into separate power domains: a low-power domain for the processor and digital peripherals, and a powered domain for the voltage regulator, bandgap reference, and I/O interface circuitry. This segmentation allows the processor to be powered down while maintaining power to the interface circuits, preserving configuration information and enabling continued interfacing with external devices.
3Use of energy by moving object
If the voltage regulator is shut down to eliminate quiescent current, then power consumption is reduced, but the regulated voltage becomes zero volts
Solution Approach 1:
Before shutting down the voltage regulator, the patent latches the regulated voltage level and configuration states into hold circuits. This preliminary action ensures that when the regulator is turned off to eliminate quiescent current, the system can quickly restore the previous voltage level and configuration upon regulator reactivation, maintaining operational integrity.
Data Source
AI summary
A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.