MCU DSP Segmentation for Power Supply Filter Load
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Solution Overview
Problem
Conventional microcontroller units for digital controlled power supply systems face challenges in power efficiency and performance due to increased power consumption and larger system size, primarily because they require high CPU operating frequencies for filter operations and data processing, leading to longer sampling periods and increased costs.
Innovation Solution
A microcontroller unit with a built-in small-scale digital signal processor (DSP) that shares phase compensation calculations in the feedback control loop, allowing independent and simultaneous operation with the CPU, reducing system processing and filter operation loads, and optimizing power consumption and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating frequency of CPU core is raised to ensure processing performance for filter operation and systematic processing, then processing performance is improved, but power consumption increases
Solution Approach 1:
The invention segments the processing functions by introducing a dedicated digital signal processor (DSP) core alongside the CPU. The DSP specifically handles filter operations while the CPU manages systematic processing, allowing both to operate at optimized frequencies rather than requiring the CPU to handle all tasks at high frequency, thus reducing overall power consumption while maintaining processing performance.
Solution Approach 2:
The DSP acts as an intermediary processing unit between the ADC and PWM modules. It receives raw ADC data, performs filter operations, and outputs processed data to the PWM module, thereby offloading the CPU from intensive filter calculations and enabling the CPU to operate at lower frequencies while maintaining system performance.
2Productivity
If the operating frequency of CPU core is raised to ensure processing performance, then processing performance is improved, but power efficiency of power supply during low load conditions deteriorates
Solution Approach 1:
By segmenting processing tasks between CPU and DSP, the system can dynamically allocate resources based on load requirements. During low load conditions, only the DSP needs to operate at high frequency for filter operations while the CPU can operate at lower frequency, improving power efficiency compared to having the CPU run at high frequency continuously.
3Use of energy by moving object
If the performance of CPU is low or does not satisfy required data processing, then power consumption is reduced, but sampling period for digital control becomes longer
Solution Approach 1:
The segmentation of processing tasks allows the DSP to handle time-critical filter operations with deterministic timing, ensuring that sampling period requirements are met even when the CPU operates at lower frequencies for power efficiency. The DSP's dedicated filter processing guarantees timely data processing without being bottlenecked by CPU performance.
4Use of energy by moving object
If the sampling period for digital control becomes longer, then power consumption is reduced, but the cycle of PWM waveform cannot become short
Solution Approach 1:
By separating filter processing to the DSP, the system can maintain short PWM cycles for high-speed power conversion while the CPU operates at lower frequencies. The DSP handles the time-critical filter operations that directly impact PWM timing, allowing the PWM cycle to remain short without requiring the entire system to operate at high speeds.
Data Source
AI summary
A technology capable of reducing load on both system processing and filter operation and improving power consumption and performance is provided. In a digital signal processor, a program memory, a program counter, and a control logic circuit are provided, and a bit field of each instruction includes instruction stop flag information and bit field information. Also, the control logic circuit carries out the control in such a manner that the instruction whose instruction stop flag information is cleared is executed as is to proceed to the next instruction processing, execution of the instruction whose instruction stop flag information is set is stopped if an execution resumption trigger condition corresponding to the bit field information is not satisfied, and the instruction whose instruction stop flag information is set is executed if the execution resumption trigger condition corresponding to bit field information is satisfied, to proceed to the next instruction processing.