Microcontroller Unit EPU Segmentation for Power Control
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Solution Overview
Problem
In microcontroller units for power conversion, condition determination processes necessary for full digital power-supply control and motor control cannot be performed solely by the DSP, requiring CPU intervention, which lowers system performance due to the CPU's limited instruction execution and interrupt handling capabilities, and adding mechanisms to enhance DSP functionality increases chip area.
Innovation Solution
A microcontroller unit with a first arithmetic processing unit (CPU) and a second arithmetic processing unit (EPU) that includes a processor and memory, along with arbitration circuits to manage access to the data bus and memory, allowing the EPU to perform condition determination and other processes without CPU intervention, thereby maintaining chip area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a low-cost CPU is employed in the MCU, then the chip area and cost are reduced, but the instruction execution performance and interrupt acknowledge performance are lowered
Solution Approach 1:
The patent divides the arithmetic processing functions into two separate units: a CPU for system-level control and a DSP for real-time signal processing and condition determination. This segmentation allows each unit to be optimized for its specific function, with the DSP handling time-critical operations independently, thus maintaining high instruction execution performance while using a simpler, lower-cost CPU core
Solution Approach 2:
The patent introduces a DMAC (Direct Memory Access Controller) as an intermediary component that enables the DSP to access memory and peripheral devices independently without CPU intervention. This mediator allows the DSP to execute arithmetic processing sequences and handle interrupts autonomously, preserving high-speed real-time processing capabilities while the CPU remains simple and cost-effective
2Adaptability or versatility
If the DSP is enhanced to perform condition determination, then the condition determination capability is improved, but the chip area increases due to added mechanisms and increased instruction memory capacity
Solution Approach 1:
The patent implements a unified instruction set architecture that the DSP can execute both traditional arithmetic processing sequences and condition determination instructions. The DSP's instruction memory and execution units are designed to handle multiple types of operations (arithmetic, logic, condition determination) using the same hardware resources, avoiding the need for separate dedicated circuits for each function and thus preventing chip area expansion
Solution Approach 2:
The DSP is designed with autonomous capability to perform condition determination through its own instruction execution engine, without requiring external control or additional specialized hardware. The DSP independently fetches, decodes, and executes condition determination instructions from its instruction memory, making the chip area increase unnecessary while achieving the desired adaptability
3Adaptability or versatility
If the CPU intervenes in condition determination processes, then the condition determination can be performed, but the real-time response performance is lowered due to CPU intervention overhead
Solution Approach 1:
The patent separates condition determination functions from the CPU by implementing them as autonomous DSP operations. The DSP independently executes condition determination instructions and generates interrupts based on its own evaluation, eliminating the need for CPU intervention in real-time condition checking. This segmentation enables true real-time response as the DSP can operate at higher speeds without CPU overhead
Solution Approach 2:
The DMAC serves as an intermediary that enables the DSP to autonomously access memory and peripheral devices for condition determination operations. By mediating the DSP's independent operation, the DMAC allows the DSP to perform condition determination and generate interrupts without CPU involvement, achieving fast real-time response while the CPU remains free for other system-level tasks
Data Source
AI summary
A microcontroller unit includes: a first arithmetic processing unit, which is able to access a data bus; a second arithmetic processing unit, which includes a processor capable of accessing the data bus, and a memory. The microcontroller unit performs a data transmitting process between peripheral circuits connected to the data bus; a first arbitration circuit, which is embedded in the second arithmetic processing unit and arbitrates access to the data bus; and a second arbitration circuit, which is embedded in the second arithmetic processing unit and arbitrates access to the memory. The memory stores arithmetic processing sequences in association with event signals transmitted from the peripheral circuits, and in response to input of the event signals, the processor executes the arithmetic processing sequences corresponding to the event signals.