Redundant Microcontroller Failover via Inter-Processor Channel
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing redundant microcontroller unit (MCU) systems face challenges in efficiently detecting failures and smoothly transitioning control between MCUs on a CAN bus, leading to suboptimal bandwidth utilization and potential communication disruptions.
Innovation Solution
A processing unit with a source MCU and a backup MCU connected via a system communication bus and an inter-microprocessor communication channel, where the backup MCU monitors for failure by detecting the absence of communication messages and takes over control upon predetermined conditions, ensuring seamless handover and recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If both MCUs are connected to 2 different CAN buses and send the same information redundantly, then reliability is improved through redundancy, but bus bandwidth utilization deteriorates due to redundant CAN messages
Solution Approach 1:
The system pre-establishes a backup MCU that remains in standby mode with all necessary communication capabilities already configured. The backup MCU monitors the active MCU through inter-microprocessor communication channels and is ready to take over immediately upon failure detection, eliminating the need for redundant simultaneous transmissions while maintaining continuous communication availability.
2Reliability
If a backup MCU monitors for failure by detecting absence of communication messages, then detection reliability is improved, but response time deteriorates due to the predetermined duration waiting period
Solution Approach 1:
The backup MCU continuously monitors the communication bus and maintains readiness to take over. The system uses a predetermined duration threshold that balances false positive prevention with quick response - the backup MCU is already in position to immediately assume control once the failure condition is confirmed, minimizing the effective switchover time.
Solution Approach 2:
The system implements a feedback mechanism where the backup MCU continuously monitors for communication messages from the active MCU. When messages are absent for the predetermined duration, this feedback triggers the failover process. The inter-microprocessor communication channel provides additional feedback paths to confirm failure conditions and coordinate the switchover, ensuring both reliable detection and rapid response.
3Reliability
If the backup MCU takes over control upon failure, then system availability is improved, but complexity increases due to the need for smooth handover and return protocols
Solution Approach 1:
The inter-microprocessor communication channel serves as an intermediary mechanism between the active and backup MCUs. This dedicated communication path simplifies the handover protocol by providing a direct coordination channel for status updates, failure notifications, and control transfer acknowledgments, reducing the complexity compared to managing handovers through the public CAN bus alone.
Data Source
AI summary
Technical solutions are described for providing a redundant processor. An example processing unit includes a source processor coupled with a system communication bus via a first communication line; a backup processor coupled with the system communication bus via a second communication line; and an inter-microprocessor communication channel for communication between the source processor and the backup processor. The backup processor monitors for a failure of the source processor by monitoring the first communication line for communication messages being transmitted by the source processor. The backup processor determines a failure of the source processor in response to an absence of the communication messages on the first communication line for a predetermined duration. The backup processor, in response to a failure of the source processor, takes over control of communication of the processing unit by sending a status update on the inter-microprocessor communication channel.


