MCU Flash Memory Deep Power Down Control via Separate Pin
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Solution Overview
Problem
Existing MCU+FLASH system architectures consume unnecessary power even in deep sleep mode due to partially operational flash memory circuits, limiting their suitability for low-power applications.
Innovation Solution
A system with an MCU and flash memory that includes an additional power supply pin on the MCU, coupled to the flash memory's power supply terminal, allowing for complete power down of the flash memory during deep power down mode, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the flash memory remains partially operational during deep sleep mode, then the system can quickly wake up and resume operations, but the system consumes unnecessary power reducing battery life
Solution Approach 1:
The patent segments the power supply control by introducing a separate power supply pin (VP) for the flash memory that is independently controllable from the main power supply. This allows the flash memory to be completely powered down during deep sleep mode while maintaining the ability to quickly resume operations by simply restoring power through the VP pin, thus resolving the contradiction between low power consumption and quick wake-up capability
Solution Approach 2:
The patent implements preliminary action by maintaining the flash memory in a partially powered state during deep sleep mode, keeping essential circuits alive and ready. This preliminary preparation allows the system to quickly transition from deep sleep to full operation without the need for complete re-initialization, thereby reducing wake-up time while still achieving significant power savings compared to full operation mode
2Use of energy by moving object
If the flash memory is completely powered down during deep sleep mode, then power consumption is minimized, but the system takes longer to enter and exit deep sleep mode
Solution Approach 1:
The patent introduces an intermediary power supply pin (VP) that mediates between the main power supply and the flash memory. This intermediary allows for granular control of power delivery, enabling the system to achieve complete power down for minimal consumption while managing the transition complexity through a dedicated control interface, thus resolving the contradiction between power minimization and control complexity
3Use of energy by moving object
If the flash memory remains operational in deep sleep mode, then data access is faster upon wake up, but unauthorized external access can occur consuming additional power
Solution Approach 1:
The patent extracts the power supply control for the flash memory from the main system power management by providing a separate, independently controllable power supply pin (VP). This extraction enables the flash memory to be completely isolated from power during deep sleep mode, preventing any unauthorized external access while still allowing rapid resumption of data access capabilities when power is restored, thus resolving the contradiction between power consumption and data protection reliability
Data Source
Figure 1~2A
Figure 2B
Figure 3A
AI summary
The present invention provides a system with an MCU and flash memory and a method for DPD control thereof. A new DPD mode (first DPD mode) is provided by simply adding a power supply pin to the MCU. The power supply pin is coupled to a power supply terminal of the flash memory. In a deep power down mode, the flash memory is configured to be entirely powered down, leading to even lower system power consumption than in a conventional DPD mode (second DPD mode).