Multi-Protocol MCU Interface Peripheral for Low-CPU Custom Protocols
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Solution Overview
Problem
Existing high-performance micro-controller chips face challenges in supporting non-consensus communication protocols, leading to inefficient CPU usage, power wastage, and frequent interruptions due to software implementation of these protocols, which are often slow and lack industry standardization.
Innovation Solution
A micro-controller chip with a multi-protocol communication interface peripheral utilizing a RISC instruction set micro-kernel and SRAM code memory to dynamically load I/O port control programs, enabling flexible support for various communication protocols, reducing hardware requirements and optimizing CPU usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software implementation is used for non-consensus communication protocols, then protocol support flexibility is improved, but CPU time consumption increases and power efficiency deteriorates
Solution Approach 1:
The patent segments the communication interface control into two parts: a RISC micro-kernel dedicated to handling communication protocols and the main processor kernel for other tasks. This segmentation allows the RISC micro-kernel to independently manage protocol communication without occupying the main processor, thereby reducing CPU time consumption while maintaining protocol support flexibility.
Solution Approach 2:
The RISC micro-kernel acts as an intermediary between the communication interface and the main processor. It handles the protocol-specific operations and data transmission, mediating between the communication requirements and the main processor, thus freeing the main processor from direct involvement in low-speed communication tasks.
2Adaptability or versatility
If multiple sets of redundant fixed protocol communication interfaces are provided, then protocol compatibility is improved, but hardware complexity and cost increase
Solution Approach 1:
The patent implements a universal communication interface controlled by a RISC micro-kernel that can adapt to multiple protocols through software configuration rather than requiring separate hardware interfaces for each protocol. This multi-functional approach allows a single interface to support various protocols, reducing hardware complexity while maintaining protocol compatibility.
Solution Approach 2:
The patent changes the approach from fixed hardware parameters to flexible software-configurable parameters. By allowing protocol parameters to be defined and changed through software (micro-kernel programming), the system can support multiple protocols without changing the underlying hardware structure, thus reducing hardware complexity.
3Speed
If interrupt method is used for non-consensus protocol implementation, then real-time response is improved, but system efficiency deteriorates due to frequent interruptions
Solution Approach 1:
The patent segments the processing of communication interrupts from the main processor by implementing an independent RISC micro-kernel that handles communication protocol interrupts autonomously. This segmentation ensures real-time response to communication events while preventing frequent interruptions to the main processor, thereby maintaining system efficiency.
Data Source
AI summary
Disclosed are a micro-controller chip containing a multi-protocol communication interface peripheral and an operation method thereof. The micro-controller chip comprises a multi-protocol communication interface peripheral, the multi-protocol communication interface peripheral is connected to a system bus, the multi-protocol communication interface peripheral is connected with an I/O port, the multi-protocol communication interface peripheral comprises an exclusively used RISC instruction set micro-kernel, a code memory and a code program stored on the code memory and executable by the RISC instruction set micro-kernel, the code program at least comprises two bit operation instructions of 1 setting and 0 clearing, the instructions are single-cycle instructions, and when the RISC instruction set micro-kernel executes the code program, the I/O port outputs 1 or 0.