MCU Memory Allocation Between RAM and Flash for Execution Speed
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Solution Overview
Problem
Microcontroller units (MCUs) face challenges in efficiently executing software due to limitations in internal and external flash memory configurations, leading to performance issues and reduced flexibility in capacity, with internal flash being less configurable and external flash causing execution speed degradation.
Innovation Solution
A method for allocating portions of application software to execute from either RAM or flash memory based on performance and capacity requirements, determined by a computing device analyzing execution metrics and capacity data to optimize memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If internal flash memory is used to store software instructions and data, then execution speed and latency are improved, but memory capacity and configurability are reduced
Solution Approach 1:
The patent segments software into different portions and allocates them to different memory types (internal flash, external flash, RAM) based on execution frequency and capacity requirements. Frequently executed portions are placed in internal flash for speed, while less frequently executed portions are placed in external flash to conserve internal memory capacity.
Solution Approach 2:
The patent applies local quality by assigning different storage locations to different portions of software based on their specific characteristics. Critical time-sensitive code is stored in internal flash with high-speed access, while bulk data and less critical code are stored in external flash or RAM, optimizing both speed and capacity utilization.
2Quantity of substance
If external flash memory is used to increase memory capacity, then software size limitations are removed, but execution speed and latency are degraded
Solution Approach 1:
The patent divides software into time-critical portions and non-time-critical portions, placing the former in internal flash for fast execution and the latter in external flash for expanded capacity. This segmentation allows the system to achieve both high speed for critical operations and large capacity for overall software storage.
Solution Approach 2:
The patent introduces RAM as an intermediary memory layer between internal flash and external flash. Data can be pre-loaded from external flash into RAM or internal flash before execution, acting as a buffer that provides both the capacity of external storage and the speed of internal memory for frequently accessed data.
3Productivity
If higher performance processing cores are used, then processing capability is improved, but available area for internal flash memory is reduced
Solution Approach 1:
The patent creates a universal memory architecture that can accommodate different processing core configurations. By supporting flexible allocation across internal flash, external flash, and RAM, the system can adapt to various MCU designs whether they prioritize processing power or internal memory capacity, making the solution applicable to a wide range of hardware configurations.
4Productivity
If multiple processing cores are employed, then computational power is improved, but area available for internal flash memory is reduced
Solution Approach 1:
The patent segments the memory architecture to serve multiple processing cores efficiently. Each core can access allocated portions of software from appropriate memory types, with the linker assigning code segments to internal flash for critical functions and to external flash/RAM for less time-sensitive operations, thereby supporting multi-core performance while managing limited internal flash resources.
Data Source
AI summary
Various examples disclosed herein relate to allocation of code and data of application software among memory of a microcontroller unit (MCU), and more particularly to allocating portions of the application software to random access memory or flash memory of an MCU based on information associated with of each portion of the application software. A method is provided herein that comprises instructing an MCU to execute an application software. The method further comprises obtaining information indicative of a performance of portions of the application software on the MCU and capacity requirements of the portions of the application software, and designating, based on the information, each of the portions of the application software for execution from either a first memory or a second memory when deployed to one or more MCUs.