MCU Memory Controller ECC Modes for Soft-Failure Recovery
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Solution Overview
Problem
Conventional MCU systems face significant performance degradation due to soft failures in cache and buffer memories, leading to system resets and inefficient operation when multiple bit errors exceed the error correction capability of ECC logic, resulting in unnecessary data transfer and operational interruptions.
Innovation Solution
A memory controller with an ECC logic module and a smart load controller (SLC) that dynamically selects error correction modes based on ECC error conditions and soft failure locations, allowing for real-time error correction and handling of soft failures by overwriting, refreshing, or invalidating memory locations, thereby maintaining system continuity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC logic with SEC-DED capabilities is used to detect and correct bit errors, then reliability is improved, but productivity deteriorates when multiple bit errors exceed correction ability
Solution Approach 1:
The patent segments the error correction process into multiple modes: ECC correction mode for correctable errors, uncorrectable error handling mode for errors beyond ECC capability, and system reset mode for critical failures. This segmentation allows the system to handle different error scenarios appropriately, maintaining productivity for correctable errors while ensuring reliability for uncorrectable errors.
Solution Approach 2:
The patent implements dynamic error handling by switching between different operational modes based on the type and severity of errors detected. The system dynamically adjusts its response - using ECC correction when possible, transitioning to uncorrectable error handling when ECC fails, and resorting to system reset only when necessary. This dynamic approach resolves the contradiction by optimizing both reliability and productivity based on real-time error conditions.
2Reliability
If system reset is triggered when ECC correction fails, then reliability is improved, but loss of time increases due to unnecessary data transfer
Solution Approach 1:
The patent implements preliminary action by pre-establishing uncorrectable error handling modes that can be activated without full system reset. The system prepares alternative execution paths and data sources in advance, allowing it to respond to uncorrectable errors by switching to backup mechanisms rather than immediately triggering a complete system reset and retransfer of all data.
Solution Approach 2:
The patent extracts the error handling function from the monolithic system reset operation. Instead of treating all errors uniformly with a complete system reset, the system separates correctable errors (handled by ECC) from uncorrectable errors (handled by dedicated uncorrectable error handling mode), allowing selective recovery without unnecessary system-wide interruption and data retransfer.
3Productivity
If cache and buffer capacity is increased to improve performance, then productivity is improved, but reliability deteriorates due to higher soft-failure probability
Solution Approach 1:
The patent applies beforehand cushioning by implementing comprehensive error detection and correction mechanisms (ECC logic) in advance within the cache and buffer systems. This protective layer is built into the memory architecture before soft failures occur, allowing the system to handle a higher capacity cache and buffer while maintaining reliability through proactive error correction and detection capabilities.
Data Source
AI summary
A memory controller (MC) and a microcontroller unit (MCU) chip are disclosed. The MC is obtained by adding a smart load control (SLC) module to an MC architecture with an ECC logic module. When a CPU is reading contents from first memory, the ECC logic module can accurately identify soft failure locations and correct 1, 2 or more bit errors, and when errors exceeding the error correction ability of the ECC logic module, the SLC module can select a suitable error correction mode for handling the soft failures in the first memory based on conditions of different ECC errors and soft failure locations as well as on the system's error correction need.