MCU Memory Fault Detection via Interface Circuit Check Words
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Solution Overview
Problem
Existing methods for detecting errors in memory usage by control units in apparatuses are slow and may not promptly trigger the stop procedure for power circuits, especially when errors occur during main task operations, leading to potential malfunctions and delayed execution of error correction.
Innovation Solution
A method involving interface circuits that calculate check words for volatile memories and use error-correction bits for non-volatile memories to detect errors and send error signals directly to an output circuit without accessing the memory, triggering a procedure to stop power circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the control unit executes a test procedure as a background task to detect memory faults, then memory errors can be detected, but the detection is slow and may not trigger the stop procedure promptly when errors occur during main task operations
Solution Approach 1:
The patent implements preliminary error detection by calculating check words and using error-correction bits immediately when data is read from memory, before the main task proceeds. This allows errors to be detected at the moment they occur rather than waiting for periodic background testing, thus resolving the contradiction between reliability and time loss.
2Reliability
If the control unit uses existing error detection methods with interrupt routines, then errors can be detected, but the execution of the stop procedure may be disabled due to incorrect access to memory words or faults in the memory storing the routine
Solution Approach 1:
The patent extracts the error detection function from the main control unit by implementing it directly in the memory interface circuitry. The interface circuit independently calculates check words and detects errors without involving the control unit's interrupt routines or memory access mechanisms, thus avoiding the complexity and potential failures associated with the control unit's error handling path.
3Reliability
If the control unit executes test procedures to detect memory faults, then errors can be detected, but the resources of the control unit are busy with storing and executing test procedures
Solution Approach 1:
The memory interface circuit performs error detection autonomously without requiring the control unit to execute test procedures. The interface circuit self-services the error detection function by independently calculating check words and detecting errors, freeing the control unit resources for productive tasks while maintaining reliability.
Data Source
AI summary
An apparatus having a microcontroller includes a processing unit, an internal communication bus assembly, a volatile memory, a non-volatile memory, a logic error management circuit, and two interface circuits. A first interface circuit couples the processing unit to the volatile memory via the internal communication bus assembly. A second interface circuit couples the processing unit to the non-volatile memory via the internal communication bus assembly. When the microcontroller is operating, the interface circuits are arranged to retrieve and evaluate requested data from their respective memory without intervention from the processing unit. In the event a failure is detected, the logic error management circuit is arranged to assert a stop signal. In some cases, detecting a failure includes comparing a check value stored in memory with a check value calculated from the data retrieved from memory.