MCU Memory Controller with Smart ECC Recovery for Soft Failures
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Solution Overview
Problem
Conventional MCU systems face significant performance degradation due to soft failures in cache and buffer memories, which require system resets and lengthy content retransfer when ECC logic cannot correct multiple bit errors, disrupting operational continuity and efficiency.
Innovation Solution
A memory controller with an ECC logic module and a smart load controller (SLC) that dynamically selects error correction modes based on error conditions and failure locations, allowing for real-time correction and refreshing of soft failures without system resets, using a backup memory to rapidly restore correct contents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC logic module is used to detect and correct bit errors in cache/buffer memory, then reliability of the MCU system is improved, but when multiple bit errors exceed correction capability, system reset is required causing loss of time and productivity
Solution Approach 1:
The patent segments the error correction process into two levels: (1) ECC logic module handles correctable errors individually, and (2) backup memory handles uncorrectable errors by providing replacement content. This segmentation allows the system to maintain high reliability while avoiding full system resets, as the backup memory can selectively replace only the erroneous data segments rather than requiring complete system reinitialization.
Solution Approach 2:
The backup memory pre-stores correct content that corresponds to the cache/buffer memory before errors occur. When soft failures are detected, the system can immediately retrieve and replace the erroneous content from the backup memory without needing to retransfer data from external sources, significantly reducing time loss and maintaining operational continuity.
2Productivity
If cache and buffer memory capacity is increased to improve performance, then operational efficiency is improved, but soft-failure probability increases leading to more frequent errors
Solution Approach 1:
The patent implements a backup memory that pre-stores correct content as a cushion against soft failures. This cushioning mechanism allows the system to absorb and recover from errors without affecting overall operational efficiency, as the backup content is ready for immediate deployment when errors occur, preventing performance degradation despite increased cache/buffer capacity.
3Measurement precision
If conventional ECC correction is used for multiple bit errors, then error detection capability is maintained, but system operational continuity is disrupted requiring reset and retransfer
Solution Approach 1:
The patent introduces a backup memory as an intermediary between the cache/buffer memory and the system operation. When soft failures exceed ECC correction capability, the backup memory mediates by providing replacement content, allowing the system to maintain operational continuity without requiring disruptive resets. This intermediary mechanism preserves both error detection precision and system productivity.
Data Source
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AI summary
A memory controller (MC) and a microcontroller unit (MCU) chip are disclosed. The MC is obtained by adding a smart load control (SLC) module to an MC architecture with an ECC logic module. When a CPU is reading contents from first memory, the ECC logic module can accurately identify soft failure locations and correct 1, 2 or more bit errors, and when errors exceeding the error correction ability of the ECC logic module, the SLC module can select a suitable error correction mode for handling the soft failures in the first memory based on conditions of different ECC errors and soft failure locations as well as on the system's error correction need. In this way, triggering a reset whenever there are errors exceeding the error correction ability of the ECC logic module, which necessitates interrupting the ongoing execution of a program, can be circumvented, and regardless of what soft errors have occurred, rapid soft error correction can be achieved with improved operating continuity of the system. Further, high operational reliability of the system is taken into account, and various reliability needs can be addressed.