MCU Memory Controller With Time-Multiplexed Mirrored Buffer
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Solution Overview
Problem
Conventional buffer-based solutions for MCU chips increase on-chip SRAM requirements and chip cost due to the need for larger SRAM capacity to support higher performance, leading to inefficiencies and increased expenses.
Innovation Solution
A memory controller with a mirrored buffer having a capacity smaller than the NVM, time-division multiplexing the buffer according to boot settings to sequentially copy and execute contents, allowing the CPU to directly access the mirrored buffer without waiting, reducing hardware overhead and startup time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a buffer is introduced to speed up operation by copying contents from NVM, then system performance is improved, but on-chip SRAM capacity requirement increases
Solution Approach 1:
The patent divides the buffer into multiple smaller buffer regions (first buffer region, second buffer region, etc.) that can be independently managed. Each buffer region corresponds to a specific code segment in the NVM, allowing selective copying and execution. This segmentation enables the system to use smaller total SRAM capacity while maintaining performance by only loading necessary code segments into appropriate buffer regions.
Solution Approach 2:
The patent implements dynamic buffer management where the CPU can switch between different buffer regions based on execution needs. The memory controller dynamically copies code segments from NVM to the appropriate buffer region and manages the execution process. This dynamic approach allows the system to adapt SRAM usage to actual performance requirements rather than allocating fixed large SRAM capacity.
2Productivity
If larger on-chip SRAM is used to support higher performance, then code capacity increases, but chip cost increases
Solution Approach 1:
The patent segments the code storage into NVM and divides the SRAM buffer into multiple smaller regions. This allows the system to achieve high code execution capability through intelligent distribution rather than relying on a single large SRAM block, thereby reducing SRAM area requirements and associated manufacturing costs.
Solution Approach 2:
The patent uses copying of code segments from NVM to buffer regions as a key mechanism. Instead of requiring all code to be stored in SRAM simultaneously, the system copies only the necessary segments into appropriate buffer regions for execution. This copying approach enables high code capacity with reduced SRAM requirements, directly lowering chip manufacturing costs.
3Productivity
If conventional buffer-based solution is used, then code can be executed faster, but startup time increases due to large SRAM requirements
Solution Approach 1:
The patent performs preliminary actions by pre-dividing the code into segments and pre-configuring multiple buffer regions. During startup, the system can directly load the required code segment into the appropriate buffer region without needing to allocate and initialize a large SRAM space first. This preliminary segmentation and configuration reduces startup time while maintaining fast code execution capability.
Data Source
AI summary
The present invention provides a memory controller and an MCU chip, in which a mirrored buffer with a small capacity built in the MCU can be time-division multiplexed as required by actual boot settings so that contents in the NVM are copied into the mirrored buffer at different times. Moreover, a CPU can read and run the copied contents in the mirrored buffer. Additionally, new contents are copied into the mirrored buffer during or after the CPU's execution of previously copied contents in such a manner that the newly copied contents can override part or the entirety of the previous contents. With this arrangement, hardware overhead can be reduced and significant reductions in MCU chip cost can be achieved, after each POR or system reset of the MCU chip, reduced contents are copied into the mirrored buffer, compared with the prior art, significantly shortening the startup time of the system.