MCU Partial Program Redundancy for Fault Injection Detection
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Solution Overview
Problem
Existing technologies face challenges in efficiently reducing vulnerability to fault injection attacks, particularly voltage fault injection, due to the need for additional hardware components and reduced operating frequency in dual core lock systems, making it difficult to protect against such threats effectively.
Innovation Solution
An information processing apparatus and method that utilizes redundancy execution of partial programs, where output data is recorded and compared to ensure matching before proceeding to the next program execution, enhancing software-based countermeasures against fault injection attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual core lock system is used for fault injection attack countermeasures, then vulnerability to fault injection attacks is reduced, but operating frequency is greatly reduced and hardware complexity increases
Solution Approach 1:
The patent creates a copy of the critical process execution by storing output data from redundant executions in a stack data structure. Instead of requiring two simultaneously operating CPU cores, the system executes the same process multiple times sequentially and compares the output data copies to detect faults, thereby maintaining high operating frequency while achieving fault detection capability
Solution Approach 2:
The patent segments the fault detection mechanism into separate execution phases: critical processes are identified and extracted, executed redundantly with output data stored in a stack, and then compared for consistency. This segmentation allows normal non-critical processes to run without overhead, preserving overall system productivity while providing targeted protection for security-sensitive operations
2Reliability
If dual core lock system is used for fault injection attack countermeasures, then vulnerability to fault injection attacks is reduced, but device complexity increases
Solution Approach 1:
The patent replaces complex hardware redundancy (two CPU cores with comparator logic) with software-based copying of process execution. The output data from redundant executions is stored in a stack data structure and compared through software logic, eliminating the need for dedicated hardware comparator circuits and reducing overall device complexity
Solution Approach 2:
The patent makes existing single-CPU hardware resources perform multiple functions: the same CPU executes critical processes redundantly, the same memory stores both input and output data, and the same bus infrastructure transports data between execution instances. This multi-functionality eliminates the need for dedicated redundant hardware components, reducing device complexity while maintaining security effectiveness
3Measurement precision
If redundancy execution of partial programs is implemented, then detection precision for fault injection attacks is improved, but execution time increases
Solution Approach 1:
The patent applies redundancy execution selectively only to identified critical processes rather than all program executions. By identifying and isolating security-sensitive operations, the system performs excessive redundancy only where necessary for high detection precision, while allowing non-critical processes to execute normally without redundancy overhead, thereby minimizing overall execution time impact
Data Source
AI summary
A central processing unit (CPU) 20 of a micro controller unit (MCU) 10 (information processing apparatus) sequentially executes a first-partial program (Block J) and a second-partial program (Block K). The first-partial program causes the CPU 20 to perform redundancy execution of the first unique process associated with the first-partial program twice or more (Steps S202-S208 and S212-S218). Then, the first-partial program causes the CPU 20 to record each piece of output data output for each of first unique processes (unique processes J_0 and J_1) in each of the first data regions (data regions D0j and D1j) pre-allocated to each piece of output data, and permit execution of the second-partial program subsequently to the first-partial program (Step S238) when pieces of output data of the first unique process or digest values of the output data recorded in first data regions match (Steps S220 and S228).