MCU Power-On-Reset Circuit With Separated Voltage Thresholds
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Solution Overview
Problem
Existing power-on-reset circuits in Microcontroller Units (MCUs) face challenges in achieving a significant separation between voltage rise and fall detection points, with the voltage fall detection point typically being above 1 V, which is difficult to reach the threshold voltage level.
Innovation Solution
The proposed power-on-reset circuit introduces a seventh PMOS transistor PM7 as a switch transistor to differentiate control voltages during powering-on and off, allowing the voltage rise detection point to be determined by a partial voltage of the resistor and the voltage fall detection point to be directly determined by the power supply voltage, thereby achieving a hysteresis voltage greater than 1 V and reducing the voltage fall detection point to near the threshold voltage of an NMOS transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the voltage fall detection point is determined by the threshold voltage of NMOS transistor plus source drain voltage of PMOS transistor, then the circuit structure is simple, but the voltage fall detection point is above 1 V and cannot reach the threshold voltage level
Solution Approach 1:
The patent segments the voltage detection function into two independent paths: one for voltage rise detection (using resistor voltage division) and one for voltage fall detection (using PMOS transistor gate voltage). This segmentation allows each path to be optimized independently, enabling the voltage fall detection point to reach the threshold voltage level while maintaining circuit simplicity.
Solution Approach 2:
The patent introduces an intermediary PMOS transistor (fifth PMOS transistor) that acts as a mediator between the power supply voltage and the NMOS transistor gate. This intermediary allows the voltage fall detection point to be directly determined by the power supply voltage threshold rather than being elevated by the PMOS source drain voltage, while still maintaining a simple circuit structure.
2Ease of operation
If the voltage rise and fall detection points are not significantly separated, then the circuit operation is simple, but the hysteresis voltage is insufficient and the reset signal may not be generated correctly during short-period power cycling
Solution Approach 1:
The patent changes the detection parameters for voltage rise and fall by using different detection mechanisms: voltage rise is detected through resistor voltage division (determined by partial voltage of resistor), while voltage fall is detected through PMOS transistor gate voltage (directly determined by power supply voltage). This parameter change creates significant separation between detection points, ensuring reliable reset signal generation during short-period power cycling while keeping circuit operation simple.
Solution Approach 2:
The patent implements preliminary action by establishing distinct detection thresholds before power cycling occurs. The hysteresis circuit pre-configures different detection points for voltage rise and fall, ensuring that when power is cycled in short periods, the reset signal is generated correctly because the detection points are already significantly separated rather than requiring dynamic adjustment during operation.
Data Source
AI summary
The present application discloses a power-on-reset circuit, which optimizes a hysteresis circuit and a reset signal generation circuit, and introduces a seventh PMOS transistor as a switch transistor to achieve the differentiation of control voltages at a gate end of a first NMOS transistor during powering-on and off. A voltage rise detection point is determined by a partial voltage of a resistor during powering-on, while a voltage fall detection point is directly determined by a power supply voltage during powering-off. Such differentiation may achieve a significant separation between the voltage rise detection point and the voltage fall detection point, reducing the voltage fall detection point to near a threshold voltage of the first NMOS transistor, and meeting the demand for a lower voltage fall detection point, which is consistent with a practical application of the power-on-reset circuit in an MCU.