MCU Signal Detection Using Shifted 1-Point DFT
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Solution Overview
Problem
The electrical die sorting (EDS) process for radio frequency integrated circuit (RFIC) chips is time-consuming, and existing methods like embedded BIST logic face challenges in efficiently performing tests on data with signal shifts.
Innovation Solution
A micro controller unit (MCU) and communication device that perform 1-point discrete Fourier transform (DFT) computations by right-shifting data and using a method that includes a memory to store first data and a processing circuitry to generate differences between shifted and unshifted data, enabling efficient signal testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrical die sorting (EDS) process is used to test RFIC chips, then comprehensive signal testing can be performed, but the testing time becomes excessively long
Solution Approach 1:
The patent implements built-in self-test (BIST) logic within the RFIC chip that enables the chip to perform its own signal testing without requiring external EDS equipment. The test signal is generated internally, passed through the RFIC components, and evaluated using on-chip processing circuitry, allowing the chip to self-verify its functionality and significantly reducing external testing time requirements
Solution Approach 2:
The testing function is segmented into separate BIST logic modules that can independently test specific signal paths and components. This allows targeted testing of individual functional blocks within the RFIC chip, enabling comprehensive coverage without requiring time-consuming full-chip external testing for each component
2Productivity
If embedded BIST logic is used to reduce testing time, then testing speed improves, but computational overflow occurs during 1-point DFT computation
Solution Approach 1:
The 1-point DFT computation is segmented into multiple smaller computational steps that process data in divided portions. The processing circuitry performs DFT computation on segmented signal data, reducing the computational load on any single operation and preventing overflow while maintaining overall computation accuracy through cumulative result assembly
Solution Approach 2:
The patent modifies the DFT computation parameters by adjusting the number of computation points and data segmentation levels. By changing these parameters, the system achieves a balance between computational speed and precision, preventing overflow while maintaining accurate signal analysis through optimized parameter selection
3Reliability
If data is right-shifted to perform DFT computation, then computational overflow is reduced, but data precision may be affected
Solution Approach 1:
The data is segmented into multiple portions that are processed through controlled right-shifting operations. This segmentation allows the system to reduce overflow by distributing the shift operation across multiple smaller steps rather than a single large shift, maintaining precision through incremental processing while ensuring computational stability
Solution Approach 2:
The system performs preliminary data preparation including right-shifting operations before the main DFT computation. This preliminary action prevents overflow from occurring during the critical computation phase by pre-adjusting the data magnitude, while the precision is maintained through careful selection of shift amounts and subsequent compensation operations
Data Source
AI summary
A micro controller unit including: a memory configured to store first data and second data, the first data being represented in a floating point form, and the second data being obtained by sampling a signal, and processing circuitry configured to generate (1_1)-th data by right-shifting the first data by a first bit, generate a difference between the first data and the (1_1)-th data to obtain (1_2)-th data, and perform 1-point discrete Fourier transform on the (1_1)-th data, the (1_2)-th data, and the second data based on a first function.