MCU Signal Switching for SPI Slave Data Integrity
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Solution Overview
Problem
In serial interface peripheral applications, when the update procedure of a slave device fails, the slave device stores error data, leading to the master device operating abnormally due to incorrect data access.
Innovation Solution
A micro controller unit (MCU) is introduced between the master and slave devices, equipped with a first communication interface, SPI circuit, switch circuit, and switching control circuit, to manage signal transitions and verify data integrity, allowing the MCU to correct or update incorrect data in the slave device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the slave device directly stores data from the master device, then the data access is simple and fast, but the system reliability deteriorates when update procedures fail
Solution Approach 1:
The patent introduces an intermediary device (the microcontroller unit with switching control circuit) between the master device and slave device. This intermediary verifies data integrity and controls signal routing, preventing error propagation while maintaining a relatively simple overall system architecture. The intermediary adds reliability without requiring complete system redesign.
Solution Approach 2:
The switching control circuit performs preliminary verification of data integrity before the slave device stores the data. By checking data validity in advance and preparing alternative signal paths beforehand, the system prevents storing error data and maintains reliability without adding complex post-error correction mechanisms.
2Measurement precision
If the master device directly accesses the slave device, then the operation is simple, but the data integrity cannot be verified
Solution Approach 1:
The switching control circuit implements a feedback mechanism that monitors the data transmission between master and slave devices. It verifies data integrity through checksums or other validation methods and adjusts signal routing based on verification results, ensuring data precision while automating the verification process to maintain operational simplicity.
Solution Approach 2:
The microcontroller unit performs self-verification of data integrity automatically without requiring additional manual intervention. The switching control circuit autonomously determines whether to route signals based on data validity, maintaining ease of operation while enabling precise data verification.
3Productivity
If the slave device stores error data, then the data storage is continuous, but the master device cannot operate normally
Solution Approach 1:
The switching control circuit applies preliminary anti-action by preventing error data from being stored in the first place. It monitors data integrity before storage and blocks erroneous data paths, thereby maintaining both continuous operational capability and reliability without requiring error recovery procedures.
Solution Approach 2:
The system prepares alternative signal paths and verification mechanisms in advance to cushion against potential data errors. This beforehand preparation ensures that if errors occur, they can be detected and isolated before affecting master device operation, maintaining both productivity and reliability.
Data Source
AI summary
A micro controller unit coupled between a master device and a slave device and including a first communication interface, a serial peripheral interface (SPI) circuit, a switch circuit, a second communication interface, and a switching control circuit is provided. The first communication interface receives a first external signal provided by the master device. The SPI circuit is configured to generate an internal signal. The switch circuit uses a second external signal or the internal signal as an output signal according to a control signal. The second communication interface provides the output signal to the slave device. The switching control circuit generates the control signal according to the level of the first external signal.