MCU Suspend Mode Clock Switching
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Solution Overview
Problem
Microcontroller units (MCUs) face challenges in reducing power consumption during low-power applications, particularly when requiring real-time clock functionality without internal clock operation, as existing solutions continue to dissipate power even in idle states due to high-frequency clocking and internal clock requirements.
Innovation Solution
The MCU employs a suspend mode that switches between internal and external clock signals, using an asynchronous external clock to power down internal clock circuits, allowing the timer to operate independently and maintain time-stamp information without active digital section operation, thus minimizing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor operates at high clock speed (25-100 MHz), then processing capability is improved, but power consumption increases
Solution Approach 1:
The system dynamically switches between high-speed processing mode and low-power suspend mode based on operational requirements. The clock circuit transitions from driving the processor at 25-100 MHz to operating at 80 kHz or lower, adapting the processing speed to match the actual computational needs while minimizing power consumption during idle or low-activity periods
Solution Approach 2:
The processor alternates between active processing periods at high clock speed and suspend periods at low clock speed. During suspend mode, the processor enters a low-power state periodically, allowing the system to achieve average power reduction while maintaining the ability to process data at high speed when needed
2Measurement precision
If the internal clock operates continuously, then timing accuracy is improved, but power consumption increases
Solution Approach 1:
The patent extracts the timing function from the main processor clock system by implementing a separate, independent low-power clock circuit that operates specifically for the timer during suspend mode. This allows the timer to maintain accurate time-stamping capabilities using only the 80 kHz low-frequency oscillator, while the main processor clock can be reduced or halted, separating the timing function from the power-intensive processing clock
Solution Approach 2:
A dedicated low-power clock circuit acts as an intermediary between the main processor clock and the timer. This intermediary clock circuit uses the 80 kHz oscillator to drive the timer independently during suspend mode, enabling the timer to maintain accurate timing without requiring the main processor to operate at high frequency, thus mediating between timing accuracy requirements and power consumption
3Use of energy by moving object
If the processor enters deep sleep mode, then power consumption is reduced, but real-time clock functionality is lost
Solution Approach 1:
The system segments the clocking functionality into separate independent circuits: a main processor clock for high-speed operation, a separate low-power 80 kHz oscillator for timing during suspend mode, and an independent timer circuit that can operate autonomously. This segmentation allows the processor to enter deep sleep while the timer continues to accumulate time-stamps using its dedicated low-power clock source
Solution Approach 2:
The timer is designed to be self-sufficient during suspend mode by having its own independent clock source (the 80 kHz low-frequency oscillator). The timer can autonomously continue to count and generate time-stamps without requiring the main processor to remain active or provide clock signals, enabling the processor to enter deep sleep mode while the timer maintains real-time functionality on its own
4Use of energy by moving object
If clock speed is reduced to 32 kHz for low power mode, then power consumption is reduced, but sampling speed becomes unacceptable
Solution Approach 1:
The system dynamically adjusts clock speed based on operational mode: during active sampling operations, the processor operates at high clock speed (25-100 MHz) to achieve fast sampling rates, while during intervals between sampling operations, the system transitions to low-power mode with 80 kHz or 32 kHz clocking. This dynamic adaptation allows the system to achieve fast sampling when needed while minimizing power consumption during idle periods
Solution Approach 2:
The processor alternates between high-speed sampling periods and low-power idle periods. During brief active sampling windows, the processor runs at full speed to perform rapid data acquisition. Between sampling operations, the processor enters suspend mode with reduced clocking. This periodic switching enables the system to achieve high sampling rates when data acquisition is required while spending most time in low-power state, thereby reducing average power consumption
Data Source
AI summary
A microcontroller unit having a suspend mode of operation includes a processing circuit for receiving digital information and processing said received digital information. Timing circuitry generates timing signals to the processing circuit responsive to signals received from a clock circuit which generates both an internal clock signal and an external clock signal. Circuitry for controlling the selective application of a synchronized enable signal and the external clock signal to the timing circuitry. The circuitry applies the internal clock signal to the timing circuitry in at least an active mode of operation of the microcontroller unit responsive to at least one first control signal and applies the external clock signal to the timing circuitry in at least a suspend mode of operation of the microcontroller unit responsive to at least one suspend control signal.