MCU Synchronous Sampling Control for ADC-Peripheral Timing

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Solution Overview

Problem

Existing integrated circuits face challenges in synchronizing the operation of multiple peripheral devices without external logic circuitry, leading to increased latency and complexity in controlling clocked external signal sources for analog-to-digital converters.

Innovation Solution

Incorporating a synchronous sampling controller within the micro-controller unit (MCU) to provide synchronized clock signals to peripheral modules and analog-to-digital converters, eliminating the need for external logic circuitry and reducing latency by using a multi-phase clock for synchronized sampling operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If external logic circuitry is used to control clocked external signal sources for ADC, then synchronization capability is provided, but device complexity and latency increase

Engineering Contradiction:
Improvesynchronization capabilityVSAvoidexternal logic circuitry
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the synchronous sampling control functionality into the MCU by integrating a synchronous sampling controller that generates both the clock signal for peripheral modules and the timing signal for ADC sampling. This consolidation eliminates the need for separate external logic circuitry while maintaining synchronization capability between multiple ADCs and peripheral devices.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The synchronous sampling controller within the MCU performs multiple functions: it generates clock signals for peripheral modules, provides timing signals to ADCs, and coordinates sampling operations across multiple converters. This multi-functional approach replaces dedicated external synchronization logic with a versatile internal controller.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If external logic circuitry is used for ADC synchronization, then sampling coordination is achieved, but latency increases

Engineering Contradiction:
Improvesampling coordinationVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

By combining the clock generation and sampling timing control functions into a single synchronous sampling controller within the MCU, the patent eliminates signal propagation delays through external logic circuitry. The integrated controller directly provides coordinated timing signals to multiple ADCs, reducing latency while maintaining sampling coordination.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If additional I/O pins and interrupt mechanisms are used for peripheral control, then control functionality is enhanced, but device complexity increases

Engineering Contradiction:
Improvecontrol functionalityVSAvoidI/O pins and interrupt mechanisms
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The synchronous sampling controller provides versatile control functionality for multiple peripheral modules and ADCs using a unified timing mechanism. This approach maintains adaptability and control capabilities while avoiding the need for additional dedicated I/O pins and interrupt mechanisms for each peripheral device.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20130222027A1Integrated circuit, micro-controller unit, and method including a synchronous sampling controller
Publication Date: 2013.08.29 SILICON LABORATORIES INC
  • US20130222027A1 patent drawing
  • US20130222027A1 patent drawing
  • US20130222027A1 patent drawing

AI summary

A micro-controller unit (MCU) includes an analog-to-digital converter (ADC) including an input, a timing input, and an output. The input of the ADC is configurable to couple to an output of a peripheral module. The MCU further includes a synchronous sampling controller configured to provide a clock signal to a clock output terminal configurable to couple to a clock input of the peripheral module. The synchronous sampling controller is further configured to provide a timing signal to the timing input of the ADC to synchronize sampling of a signal at the input of the ADC to timing of the peripheral module.