MDAC Time-Interleaved ADC Architecture for Skew Error Correction
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Solution Overview
Problem
High-speed and high-accuracy analog-to-digital converters (ADCs) face challenges in designing due to speed and accuracy requirements, particularly in low power solutions, with time-interleaved stages prone to errors from clock skew, gain, and offset issues, leading to accuracy degradation in digital conversion.
Innovation Solution
The implementation of a multi-stage ADC architecture using a front-end multiplying digital-to-analog converter (MDAC) and an array of current-controlled ring oscillator (ICRO) sub-ADCs, with efficient calibration techniques to correct for non-linearities and errors, providing improved isolation and linearity, and allowing for scalable performance and throughput trade-offs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If time-interleaved stages are used to achieve high-speed operation, then sample rate is improved, but measurement precision deteriorates due to clock skew, gain, and offset errors
Solution Approach 1:
The ADC is divided into multiple time-interleaved sub-ADCs (first, second, and third sub-ADCs) that operate in parallel with different sampling phases. Each sub-ADC converts a portion of the input signal at a lower individual rate, but together they achieve a higher composite sample rate. This segmentation allows high-speed operation while maintaining accuracy through proper combining of the parallel conversion results.
2Productivity
If time-interleaved stages are used to increase throughput, then productivity is improved, but reliability deteriorates due to sampling errors and spurious noise
Solution Approach 1:
A feedback mechanism is implemented where the conversion results from the multiple sub-ADCs are combined and processed to generate correction values. These correction values are used to adjust and compensate for gain, offset, and timing errors in each sub-ADC. The feedback loop continuously monitors and corrects errors, ensuring high reliability and accuracy while maintaining high throughput through parallel operation.
3Speed
If multiple sub-ADCs are used to achieve high sample rates, then speed is improved, but device complexity increases due to clock skew control requirements
Solution Approach 1:
The system uses periodic sampling with distinct phases for each sub-ADC. The first sub-ADC samples during a first phase, the second sub-ADC samples during a second phase, and the third sub-ADC samples during a third phase. This periodic, phase-based operation simplifies clock control by using regular, repeating patterns rather than requiring complex arbitrary timing control, reducing device complexity while achieving high sample rates.
Data Source
AI summary
Time-interleaved analog-to-digital converters (ADCs) and related methods are disclosed that are based upon multiplying digital-to-analog converters (MDACs). For one ADC embodiment, a sample-and-hold circuit receives an input signal and outputs a voltage that represents the input signal. An MDAC receives the voltage, outputs an N-bit digital value, and outputs a current that represents the voltage. A phased current generator receives the current and outputs time-interleaved currents that are based upon the current. An array of sub-ADCs receive the time-interleaved currents, and each sub-ADC outputs a digital value. The digital values from the array of sub-ADCs are then combined and to output an M-bit digital value. The N-bit digital value and the M-bit digital value provide a digital conversion output for the ADC.