MDAC Time-Interleaved ADC Architecture for Skew Error Reduction
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Solution Overview
Problem
High-speed and high-accuracy analog-to-digital converters (ADCs) face challenges in designing low power solutions due to issues like clock skew, gain and offset errors, and spurious noise in time-interleaved stages, which degrade the output spectrum and overall system performance.
Innovation Solution
The use of a front-end MDAC stage with an array of time-interleaved ICRO sub-ADCs, combined with efficient calibration techniques, to reduce linearity requirements and correct non-linearities, providing improved isolation and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If time-interleaved stages are used to achieve high-speed conversion, then sample rate is improved, but clock skew and gain/offset errors degrade measurement precision
Solution Approach 1:
The ADC is divided into multiple time-interleaved sub-ADCs, each operating at a lower sample rate but contributing to the overall high sample rate through parallel processing. This segmentation allows achieving high speed while reducing the burden on individual channels, thereby mitigating clock skew and gain/offset errors.
Solution Approach 2:
A calibration mechanism is implemented that uses feedback to detect and correct gain and offset errors in each time-interleaved sub-ADC. By continuously monitoring and adjusting for these errors, the system maintains high measurement precision despite the use of multiple parallel channels operating at high speeds.
2Productivity
If time-interleaved stages are used to increase throughput, then productivity is improved, but device complexity increases due to tight clock skew control requirements
Solution Approach 1:
Clock skew compensation is performed in advance through a calibration process that establishes correction factors before normal operation. This preliminary action eliminates the need for complex real-time clock skew control during high-speed conversion, simplifying the device while maintaining high throughput.
Solution Approach 2:
The system dynamically adjusts calibration parameters to optimize performance across different operating conditions. By changing parameters such as gain and offset correction values based on measured errors, the system maintains high throughput without requiring overly complex fixed clock skew control mechanisms.
3Speed
If multiple time-interleaved sub-ADCs are used to achieve high sample rates, then speed is improved, but power consumption increases
Solution Approach 1:
Instead of all sub-ADCs operating at full capacity simultaneously, the system uses partial action by activating only the necessary number of sub-ADCs based on the required sample rate and throughput. This reduces unnecessary power consumption while still achieving the desired high sample rate when needed.
Solution Approach 2:
The system dynamically changes operating parameters such as the number of active sub-ADCs and their individual conversion rates to optimize the power-speed tradeoff. By adjusting these parameters based on real-time demands, the system achieves high sample rates only when necessary, reducing overall power consumption.
Data Source
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AI summary
Time-interleaved analog-to-digital converters (ADCs) and related methods are disclosed that are based upon multiplying digital-to-analog converters (MDACs). For one ADC embodiment, a sample-and-hold circuit receives an input signal and outputs a voltage that represents the input signal. An MDAC receives the voltage, outputs an N-bit digital value, and outputs a current that represents the voltage. A phased current generator receives the current and outputs time-interleaved currents that are based upon the current. An array of sub-ADCs receive the time-interleaved currents, and each sub-ADC outputs a digital value. The digital values from the array of sub-ADCs are then combined and to output an M-bit digital value. The N-bit digital value and the M-bit digital value provide a digital conversion output for the ADC.