Switched-Capacitor MDAC Feed-Forward Amplifier for Higher Bandwidth
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Solution Overview
Problem
Conventional switched-capacitor MDAC amplifiers in high-speed CMOS pipeline ADCs face limitations in power efficiency and clock rate due to significant parasitic capacitance and non-dominant poles within the feedback loop, leading to reduced settling time and increased power consumption.
Innovation Solution
The implementation of a feed-forward approach with a common gate amplifier to buffer the input capacitor, cascode compensation, and the use of buffers to reduce parasitic capacitance, thereby improving the local feedback factor and eliminating global feedback, which enhances bandwidth and reduces power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional global feedback is used in MDAC amplifier, then system stability can be maintained, but bandwidth is limited and power consumption increases due to parasitic capacitance terms in the feedback loop
Solution Approach 1:
The patent extracts and removes the parasitic capacitance terms (input capacitance and feedback capacitance) from the global feedback loop by using a feed-forward approach. The summing node is decoupled from the feedback path, eliminating the harmful capacitance terms that limit bandwidth and increase power consumption while maintaining system stability through local feedback mechanisms.
Solution Approach 2:
The patent introduces an intermediate summing node that acts as a mediator between the input and feedback paths. This summing node is connected to the virtual ground through a resistor rather than being part of the global feedback loop, allowing the feedback signal to be summed without including the parasitic capacitance terms, thus improving bandwidth and reducing power consumption.
2Speed
If parasitic capacitance is reduced in the feedback loop, then bandwidth improves, but system stability and sensitivity control become more difficult
Solution Approach 1:
The patent segments the feedback system into separate paths: a local feedback path for stability control and a feed-forward path for signal summation. By dividing the system into these independent paths, the parasitic capacitance is removed from the global feedback loop while local feedback mechanisms maintain system stability, and sensitivity is controlled through the segmented architecture.
3Productivity
If settling time is reduced for high-speed operation, then clock rate increases, but power consumption increases due to the need for higher gain and bandwidth
Solution Approach 1:
The patent converts the harmful effect of parasitic capacitance into a benefit by using a feed-forward approach where the parasitic capacitance terms are completely removed from the feedback loop. This eliminates the need for high power consumption to compensate for capacitance-induced bandwidth limitations, allowing high clock rates to be achieved with reduced power consumption.
Data Source
AI summary
A multiplying analog-to-digital converter (“MDAC”) that reduces the power consumption of the MDAC by at least 2.3 times by improving the feedback factor. The amplifier may include a feed forward approach in which the input capacitor (also referred to as “sampling capacitor”) is buffered by a common gate amplifier to improve bandwidth by removing input and parasitic capacitance terms from the global feedback loss. THe amplifier may also use an alternate form of local compensation, for example, cascode compensation. The amplifier may also further include an alternate way to reduce parasitic capacitance with a buffer.