MDAC Reference Voltage Shifting for Compact Pipelined ADCs
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Solution Overview
Problem
Conventional pipelined analog-to-digital converters (ADCs) face limitations in design flexibility and circuit area due to the fixed requirements for reference voltages, which restrict the operation of multiplying digital-to-analog converters (MDACs) and occupy large circuit areas.
Innovation Solution
The proposed MDAC design for pipelined ADCs incorporates operational amplifiers and capacitors that allow for the shifting and scaling of reference voltages without affecting the MDAC's operation, enabling greater design flexibility and reducing the overall circuit area by allowing one of the reference voltages to be set to ground, thereby eliminating the need for a unity gain buffer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reference voltages are designed with fixed requirements (VREF+−VREF−=0.5Vpp_max and VCM_REF=VCM_PGA), then the pipelined ADC operates stably, but the design flexibility of reference voltages is limited and the circuit area increases due to large unit gain buffers
Solution Approach 1:
The patent introduces a dynamic reference voltage generation mechanism where the common-mode voltage VCM_OPI is shifted by an offset voltage Voffset. This dynamic adjustment allows the reference voltages to adapt to different operating conditions while maintaining stability, resolving the contradiction between fixed requirements and design flexibility
Solution Approach 2:
The patent changes the parameter relationships by introducing Voffset such that VCM_OPI−Voffset=VCM_REF. This parameter transformation allows the reference voltages to be generated with flexible common-mode levels while maintaining the required voltage difference, enabling both stability and adaptability
2Reliability
If the reference voltages are designed with fixed requirements (VREF+−VREF−=0.5Vpp_max and VCM_REF=VCM_PGA), then the pipelined ADC operates stably, but the circuit area increases due to large unit gain buffers
Solution Approach 1:
The dynamic reference voltage generation eliminates the need for large unit gain buffers by using a compact offset voltage addition circuit. This reduces the circuit area significantly while maintaining stable operation through the dynamic adjustment mechanism
Solution Approach 2:
The patent uses a simplified reference voltage generation approach that copies only the essential function of generating VREF+ and VREF− with the correct voltage difference, eliminating the need for bulky buffer circuits while maintaining operational stability
Data Source
AI summary
This invention discloses a multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (pipelined ADC). The MDAC includes an operational amplifier. The MDAC samples a differential input signal in a sampling phase and performs subtraction and multiplication operations in an amplification phase according to a first reference voltage and a second reference voltage. The common-mode voltage of the first reference voltage and the second reference voltage is not substantially equal to the common-mode voltage of the differential input signal; and/or the voltage difference between the first reference voltage and the second reference voltage is not substantially equal to one half of an allowed maximum peak-to-peak value of the differential input signal. One of the first reference voltage and the second reference voltage can be ground.